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PDF AS7C3256A-12JI Data sheet ( Hoja de datos )
| Número de pieza | AS7C3256A-12JI | |
| Descripción | 5V/3.3V 32K X 8 CMOS SRAM (Common I/O) | |
| Fabricantes | ETC | |
| Logotipo |  |
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March 2001
Advance Information
AS7C256A
AS7C3256A
®
5V/3.3V 32K X 8 CMOS SRAM (Common I/O)
Features
• AS7C256A (5V version)
• AS7C3256A (3.3V version)
• Industrial and commercial temperature
• Organization: 32,768 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Very low power consumption: ACTIVE
- 495mW (AS7C256A) / max @ 10 ns
- 216mW (AS7C3256A) / max @ 10 ns
• Very low power consumption: STANDBY
- 11 mW (AS7C256A) / max CMOS I/O
- 3.6 mW (AS7C3256A) / max CMOS I/O
• Latest 6T 0.25u CMOS technology
• 2.0V data retention
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 300 mil SOJ
- 8 × 13.4 TSOP
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
VCC
GND
A0
A1
A2
A3
A4
A5
A6
A14
Input buffer
256 X 128 X 8
Array
(262,144)
Column decoder
AAAAAAA
7 8 9 10 11 12 13
Control
circuit
Pin arrangement
28-pin TSOP I (8×13.4)
28-pin SOJ (300 mil)
I/O7
I/O0
WE
OE
CE
OE 1 (22)
(21) 28 A10
A11 2 (23)
(20) 27 CE
A9 3 (24)
(19) 26 I/O7
A8 4 (25)
(18) 25 I/O6
A13 5 (26)
(17) 24 I/O5
WE 6 (27)
(16) 23 I/O4
VCC
A14
A12
7
8
9
(28)
(1)
(2)
AS7C256A
AS7C3256A
(15) 22
(14) 21
(13) 20
I/O3
GND
I/O2
A7 10 (3)
(12) 19 I/O1
A6 11 (4)
(11) 18 I/O0
A5 12 (5)
(10) 17 A0
A4 13 (6)
(9) 16 A1
A3 14 (7)
(8) 15 A2
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
Selection guide
Maximum address access time
Maximum output enable access time
AS7C256A
Maximum operating current
AS7C3256A
Maximum CMOS standby
current
AS7C256A
AS7C3256A
AS7C256A-10
AS7C3256A-10
10
3
90
60
2
1
AS7C256A-12
AS7C3256A-12
12
3
80
50
2
1
AS7C256A-15
AS7C3256A-15
15
4
70
45
2
1
AS7C256A-20
AS7C3256A-20
20
5
70
45
5
2
Unit
ns
ns
mA
mA
mA
mA
3/7/01; V.0.9.2
Alliance Semiconductor
P. 1 of 8
Copyright © Alliance Semiconductor. All rights reserved.
1 page  
AS7C256A
AS7C3256A
®
Write cycle (over the operating range)11
-10 -12 -15 -20
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Write cycle time
Chip enable to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Shaded areas contain advance information.
tWC
tCW
tAW
tAS
tWP
tAH
tDW
tDH
tWZ
tOW
10 - 12 – 15 – 20 –
ns
8 - 10 – 12 – 12 – ns
8 - 9 – 10 – 12 – ns
0 -- 0 – 0 – 0 –
ns
7 - 8 – 9 – 12 – ns
0 - 0 – 0 – 0 – ns
5 - 6 – 8 – 10 – ns
0 - 0 – 0 – 0 – ns 4, 5
- 6 – 6 – 6 – 6 ns 4, 5
1 - 1 – 1 – 2 – ns 4, 5
Write waveform 1 (WE controlled)10,11
Address
tWC
tAW
WE
tAS
tWP
Din
tWZ
Dout
tAH
tDW
Data valid
tOW
tDH
Write waveform 2 (CE controlled)10,11
tWC
tAW
Address
CE
WE
tAS tCW
tWP
tWZ
Din
Dout
tDW
Data valid
tAH
tDH
3/7/01; V.0.9.2
Alliance Semiconductor
P. 5 of 8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AS7C3256A-12JI.PDF ] | |
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