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PDF AS7C31024A-10TI Data sheet ( Hoja de datos )
| Número de pieza | AS7C31024A-10TI | |
| Descripción | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) | |
| Fabricantes | ETC | |
| Logotipo |  |
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January 2001
Advance Information
AS7C1024A
AS7C31024A
®
5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
Features
• AS7C1024A (5V version)
• AS7C31024A (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,012 words x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Low power consumption: ACTIVE
- 660 mW (AS7C1024A) / max @ 10 ns
- 324 mW (AS7C31024A) / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS
- 36 mW (AS7C31024A) / max CMOS
• Latest 6T 0.25u CMOS technology
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
VCC
GND
Input buffer
A0
A1
A2
A3
512×256×8
A4 Array
A5
A6
(1,048,576)
A7
A8
Column decoder
Control
circuit
I/O7
I/O0
WE
OE
CE1
CE2
Pin arrangement
32-pin TSOP I
(8 x 20mm)
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15 7
VNCCC
8
9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
32
31
30
OE
A10
CE1
NC
A16
29 I/O7 A14
28 I/O6 A12
27 I/O5 A7
26 I/O4 A6
25 I/O3 A5
24
23
22
21
20
19
GND
I/O2
I/O1
I/O0
A0
A1
A4
A3
A2
A1
A0
18 A2 I/O0
17 A3 I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Selection guide
Maximum address access time
Maximum output enable access time
Maximum
ASAS7C1024A
operating current AS7C31024A
Maximum CMOS
standby current
AS7C1024A
AS7C31024A
AS7C1024A-10
AS7C31024A-10
10
3
120
90
10
10
AS7C1024A-12
AS7C31024A-12
12
3
110
80
10
10
AS7C1024A-15
AS7C31024A-15
15
4
100
80
10
10
AS7C1024A-20
AS7C31024A-20
20
5
100
80
15
15
Unit
ns
ns
mA
mA
mA
mA
2/6/01; V.0.9
Alliance Semiconductor
P. 1 of 8
Copyright © Alliance Semiconductor. All rights reserved.
1 page  
AS7C1024A
AS7C31024A
®
Write cycle (over the operating range)11, 12
-10
Parameter
Symbol Min Max
Write cycle time
tWC 10 –
Chip enable (CE1) to write end
tCW1
8
–
Chip enable (CE2) to write end tCW2 8 –
Address setup to write end
tAW 8 –
Address setup time
tAS 0 –
Write pulse width
tWP 7 –
Address hold from end of write tAH 0 –
Data valid to write end
tDW 5 –
Data hold time
tDH 0 –
Write enable to output in high Z tWZ – 6
Output active from write end
tOW 1 –
-12
Min Max
12 –
10 –
10 –
9–
0–
8–
0–
6–
0–
–6
1–
-15
Min Max
15 –
12 –
12 –
10 –
0–
9–
0–
8–
0–
–6
1–
-20
Min Max
20 –
12 –
12 –
12 –
0–
12 –
0–
10 –
0–
–8
2–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
12
12
4, 5
4, 5
4, 5
Write waveform 1 (WE controlled)10,11,12
Address
tWC
tAW
WE
tAS
tWP
DIN
tWZ
DOUT
tAH
tDW
Data valid
tOW
tDH
Write waveform 2 (CE1 and CE2 controlled)10,11,12
tWC
tAW
Address
tAS tCW1, tCW2
CE1
CE2
tWP
WE
tWZ tDW
DIN Data valid
DOUT
tAH
tDH
2/6/01; V.0.9
Alliance Semiconductor
P. 5 of 8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AS7C31024A-10TI.PDF ] | |
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