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PDF AD7713 Data sheet ( Hoja de datos )
| Número de pieza | AD7713 | |
| Descripción | LC2MOS Loop-Powered Signal Conditioning ADC | |
| Fabricantes | Analog Devices | |
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a
LC2MOS
Loop-Powered Signal Conditioning ADC
AD7713*
FEATURES
Charge Balancing ADC
24 Bits No Missing Codes
؎0.0015% Nonlinearity
Three-Channel Programmable Gain Front End
Gains from 1 to 128
Two Differential Inputs
One Single Ended High Voltage Input
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Single Supply Operation
Low Power (3.5 mW typ) with Power-Down Mode
(150 W typ)
APPLICATIONS
Loop Powered (Smart) Transmitters
RTD Transducers
Process Control
Portable Industrial Instruments
GENERAL DESCRIPTION
The AD7713 is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a transducer or high level signals (4 × VREF) and
outputs a serial digital word. It employs a sigma-delta con-
version technique to realize up to 24 bits of no missing codes
performance. The input signal is applied to a proprietary pro-
grammable gain front end based around an analog modulator.
The modulator output is processed by an on-chip digital filter.
The first notch of this digital filter can be programmed via the
on-chip control register allowing adjustment of the filter cutoff
and settling time.
The part features two differential analog inputs and one single-
ended high level analog input as well as a differential reference
input. It can be operated from a single supply (AVDD and DVDD
at +5 V). The part provides two current sources which can be
used to provide excitation in three-wire and four-wire RTD con-
figurations. The AD7713 thus performs all signal conditioning
and conversion for a single, dual or three-channel system.
The AD7713 is ideal for use in smart, microcontroller-based
systems. Gain settings, signal polarity and RTD current control
can be configured in software using the bidirectional serial port.
The AD7713 contains self-calibration, system calibration and
background calibration options and also allows the user to read
and to write the on-chip calibration registers.
*Protected by U.S. Patent No. 5,134,401.
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
AIN3
RTD1
RTD2
FUNCTIONAL BLOCK DIAGRAM
REF REF
AVDD DVDD IN(–) IN(+)
VBIAS
STANDBY
AVDD
AD7713
1µA
CHARGING BALANCING A/D
CONVERTER
INPUT
SCALING
M PGA
AUTO-ZEROED
∑−∆
MODULATOR
DIGITAL
FILTER
U
X
A = 1 – 128
CLOCK
GENERATION
200µA AVDD
200µA
SERIAL INTERFACE
CONTROL
REGISTER
OUTPUT
REGISTER
SYNC
MCLK
IN
MCLK
OUT
AGND DGND RFS TFS MODE SDATA SCLK DRDY A0
CMOS construction ensures low power dissipation and a hard-
ware programmable power-down mode reduces the standby
power consumption to only 150 µW typical. The part is avail-
able in a 24-pin, 0.3 inch wide, plastic and hermetic dual-in-line
package (DIP) as well as a 24-lead small outline (SOIC) package.
PRODUCT HIGHLIGHTS
1. The AD7713 consumes less than 1 mA in total supply cur-
rent, making it ideal for use in loop-powered systems.
2. The two programmable gain channels allow the AD7713 to
accept input signals directly from a transducer removing a
considerable amount of signal conditioning. To maximize the
flexibility of the part, the high level analog input accepts
4 × VREF signals. On-chip current sources provide excitation
for three-wire and four-wire RTD configurations.
3. No Missing Codes ensures true, usable, 24-bit dynamic
range coupled with excellent ± 0.0015% accuracy. The effects
of temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.
4. The AD7713 is ideal for microcontroller or DSP processor
applications with an on-chip control register which allows
control over filter cutoff, input gain, signal polarity and cali-
bration modes. The AD7713 allows the user to read and
write the on-chip calibration registers.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD7713
Parameter
Limit at TMIN, TMAX
(A, S Versions)
Units
Conditions/Comments
External-Clocking Mode
fSCLK
t20
t21
t22
t23
t246
t256
t26
t27
t28
t297
t30
t317
t32
t33
t34
t35
t36
fCLK IN/5
0
0
2 × tCLK IN
0
4 × tCLK IN
10
2 × tCLK IN + 20
2 × tCLK IN
2 × tCLK IN
tCLK IN + 10
10
tCLK IN + 10
10
5 × tCLK IN/2 + 50
0
0
4 × tCLK IN
2 × tCLK IN – SCLK High
30
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Serial Clock Input Frequency
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Falling Edge to DRDY High
SCLK to Data Valid Hold Time
RFS/TFS to SCLK Falling Edge Hold Time
RFS to Data Valid Hold Time
A0 to TFS Setup Time
A0 to TFS Hold Time
SCLK Falling Edge to TFS Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
NOTES
1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 10 to 13.
3CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.
4The AD7713 is production tested with fCLK IN at 2 MHz. It is guaranteed by characterization to operate at 400 kHz.
5Specified using 10% and 90% points on waveform of interest.
6These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
7These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
2
1.6mA
TO OUTPUT
PIN
100pF
+2.1V
200µA
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
REV. C
–5–
5 Page 
AD7713
Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar in-
put ranges with a VREF of +2.5 V. These numbers are typical and are generated with an analog input voltage of 0 V. The output
noise from the part comes from two sources. First, there is the electrical noise in the semiconductor devices used in the implementa-
tion of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quantization noise
is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at an even lower
level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter notch settings
(below 12 Hz approximately) tend to be device noise dominated while higher notch settings are dominated by quantization noise.
Changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement
in noise performance than it does in the device noise dominated region as shown in Table I. Furthermore, quantization noise is
added after the PGA, so effective resolution is independent of gain for the higher filter notch frequencies. Meanwhile, device noise is
added in the PGA and, therefore, effective resolution suffers a little at high gains for lower notch frequencies.
At the lower filter notch settings (below 12 Hz), the no missing codes performance of the device is at the 24-bit level. At the higher
settings, more codes will be missed until at 200 Hz notch setting, no missing codes performance is only guaranteed to the 12-bit
level. However, since the effective resolution of the part is 10.5 bits for this filter notch setting, this no missing codes performance
should be more than adequate for all applications.
The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. This does not remain con-
stant with increasing gain or with increasing bandwidth. Table II shows the same table as Table I except that the output is now ex-
pressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 × VREF/GAIN, i.e., the input full scale). It is
possible to do post filtering on the device to improve the output data rate for a given –3 dB frequency and also to further reduce the
output noise (see Digital Filtering section).
Table I. Output Noise vs. Gain and First Notch Frequency
First Notch of
Filter and O/P –3 dB
Gain of
Data Rate1 Frequency 1
Gain of
2
Typical Output RMS Noise (µV)
Gain of
4
Gain of
8
Gain of
16
Gain of
32
Gain of Gain of
64 128
2 Hz2
5 Hz2
6 Hz2
10 Hz2
12 Hz2
20 Hz3
50 Hz3
100 Hz3
200 Hz3
0.52 Hz
1.31 Hz
1.57 Hz
2.62 Hz
3.14 Hz
5.24 Hz
13.1 Hz
26.2 Hz
52.4 Hz
1.0
1.8
2.5
4.33
5.28
13
130
0.6 × 103
3.1 × 103
0.78
1.1
1.31
2.06
2.36
6.4
75
0.26 × 103
1.6 × 103
0.48
0.63
0.84
1.2
1.33
3.7
25
140
0.7 × 103
0.33
0.5
0.57
0.64
0.87
1.8
12
70
0.29 × 103
0.25
0.44
0.46
0.54
0.63
1.1
7.5
35
180
0.25 0.25 0.25
0.41 0.38 0.38
0.43 0.4 0.4
0.46 0.46 0.46
0.62 0.6
0.56
0.9 0.65 0.65
4 2.7 1.7
25 15 8
120 70 40
NOTES
1The default condition (after the internal power-on reset) for the first notch of filter is 60 Hz.
2For these filter notch frequencies, the output rms noise is primarily dominated by device noise and as a result is independent of the value of the reference voltage.
Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is
increased since the output rms noise remains constant as the input full scale increases).
3For these filter notch frequencies, the output rms noise is dominated by quantization noise and as a result is proportional to the value of the reference voltage.
Table II. Effective Resolution vs. Gain and First Notch Frequency
First Notch of
Filter and O/P –3 dB
Gain of
Data Rate
Frequency 1
Gain of
2
Effective Resolution1 (Bits)
Gain of
4
Gain of
8
Gain of
16
Gain of
32
Gain of Gain of
64 128
2 Hz
0.52 Hz
22.5
21.5
21.5
21
20.5 19.5 18.5 17.5
5 Hz
1.31 Hz
21.5
21
21
20
19.5 18.5 17.5 16.5
6 Hz
1.57 Hz
21
21
20.5 20
19.5 18.5 17.5 16.5
10 Hz
2.62 Hz
20
20
20
19.5 19
18.5 17.5 16.5
12 Hz
3.14 Hz
20
20
20
19.5 19
18 17 16
20 Hz
5.24 Hz
18.5
18.5
18.5
18.5
18
17.5 17
16
50 Hz
13.1 Hz
15
15
15.5 15.5 15.5 15.5 15 14.5
100 Hz
26.2 Hz
13
13
13
13
13
12.5 12.5 12.5
200 Hz
52.4 Hz
10.5
10.5
11
11
11
10.5 10
10
NOTE
1Effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 × VREF/GAIN). The above table applies for
a VREF of +2.5 V and resolution numbers are rounded to the nearest 0.5 LSB.
2
REV. C
–11–
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7713.PDF ] | |
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