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PDF AD9690 Data sheet ( Hoja de datos )
| Número de pieza | AD9690 | |
| Descripción | Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
14-Bit, 1 GSPS/500 MSPS JESD204B,
Analog-to-Digital Converter
AD9690
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
2.0 W total power at 1 GSPS (default settings)
1.5 W total power at 500 MSPS (default settings)
SFDR = 85 dBFS at 340 MHz, 80 dBFS at 985 MHz
SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS),
60.5 dBFS at 985 MHz
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range
AD9690-1000: 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
AD9690-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
Programmable termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors
12-bit NCO, up to 4 cascaded half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Communications
Multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
Wideband digital predistortion
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD
(1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)
VIN+
VIN–
BUFFER
ADC 14
CORE
FD
DDC
4 SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
V_1P0
CLK+
CLK–
CONTROL
REGISTERS
CLOCK
GENERATION
JESD204B
SUBCLASS 1
CONTROL
FAST
DETECT
SYNCINB±
SYSREF±
÷2
SPI CONTROL
÷4
PDWN/
÷8 AD9690 STBY
AGND DRGND DGND SDIO SCLK CSB
Figure 1.
PRODUCT HIGHLIGHTS
1. Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
2. Buffered inputs with programmable input termination eases
filter design and implementation.
3. Two integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
4. Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
5. Programmable fast overrange detection.
6. 9 mm × 9 mm, 64-lead LFCSP.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9690
GENERAL DESCRIPTION
The AD9690 is a 14-bit, 1 GSPS/500 MSPS analog-to-digital
converter (ADC). The device has an on-chip buffer and sample-
and-hold circuit designed for low power, small size, and ease of
use. This device is designed for sampling wide bandwidth
analog signals of up to 2 GHz. The AD9690 is optimized for
wide input bandwidth, high sampling rate, excellent linearity,
and low power in a small package.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The analog input and clock signals are differential inputs. The
ADC data output is internally connected to two digital down-
converters (DDCs). Each DDC consists of four cascaded signal
processing stages: a 12-bit frequency translator (NCO), and four
half-band decimation filters.
In addition to the DDC blocks, the AD9690 has several
functions that simplify the automatic gain control (AGC)
function in the communications receiver. The programmable
Data Sheet
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed
serialized output in a variety of one-, two-, or four-lane con-
figurations, depending on the DDC configuration and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF± and
SYNCINB± input pins.
The AD9690 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.
The AD9690 is available in a Pb-free, 64-lead LFCSP and is
specified over the −40°C to +85°C industrial temperature range.
This product may be protected by one or more U.S. or international
patents
Rev. A | Page 4 of 78
5 Page 
AD9690
CSB
tDS tHIGH
tS tDH
tLOW
tCLK
tACCESS
Data Sheet
tH
SCLK DON’T CARE
DON’T CARE
SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7
D5 D4 D3 D2 D1 D0 DON’T CARE
Figure 4. Serial Port Interface Timing Diagram
Rev. A | Page 10 of 78
11 Page | ||
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| PDF Descargar | [ Datasheet AD9690.PDF ] | |
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