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PDF HI-6136 Data sheet ( Hoja de datos )
| Número de pieza | HI-6136 | |
| Descripción | Compact Multi-Terminal Device | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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November, 2016
MAMBATM: HI-6136
3.3V RT / MT MIL-STD-1553 / MIL-STD-1760
Compact Multi-Terminal Device with SPI Host Interface
GENERAL DESCRIPTION
The 3.3V CMOS HI-6136 device is a member of
Holt’s MIL-STD-1553 MAMBATM family and provides
a complete single- or multi-function interface between
a host processor and MIL-STD-1553B bus. Each IC
contains a Remote Terminal (RT) and a Bus Monitor
Terminal (MT). Any combination of the contained 1553
functions can be enabled for concurrent operation. The
enabled terminals communicate with the MIL-STD-1553
buses through a shared on-chip dual bus transceiver and
external transformers. The user allocates 16K bytes of
on-chip static RAM between devices to suit application
requirements.
• Built-in self-test for protocol logic, digital signal
paths and internal RAM.
• Optional self-initialization at reset uses external
serial EEPROM.
• ±8kV ESD Protection (HBM, all pins).
• Two temperature ranges: -40oC to +85oC, or
-55oC to +125oC with optional burn-in.
• RoHS compliant and Tin / Lead options available.
PIN CONFIGURATION (TOP)
The HI-6136 communicates with the host via a 40 MHz
4-wire serial peripheral interface (SPI). Programmable
interrupts provide terminal status to the host processor.
Circular data buffers in RAM have interrupts for rollover
and programmable “level attained”.
The HI-6136 can be configured for automatic self-
initialization after reset. A dedicated SPI port reads
data from an external serial EEPROM to fully configure
registers and RAM and optionally start execution for any
of the terminal devices.
MODE - 1
IRQ - 2
ACKIRQ - 3
MODE1760 - 4
READY - 5
VCC - 6
GND - 7
ACTIVE - 8
RTSSF - 9
AUTOEN - 10
TXINHA - 11
TXINHB - 12
HI-6136PCIF
HI-6136PCTF
HI-6136PCMF
36 - TTCLK
35 - ESCLK
34 - EECOPY
33 - ECS
32 - MOSI
31 - VCC
30 - GND
29 - MISO
28 - MTTCLK
27 - LOCK
26 - RTA4
25 - RTA3
FEATURES
• Concurrent multi-terminal operation for RT and/or
MT MIL-STD-1553B functions.
• 8K x 17-bit words internal static RAM with parity
• Autonomous terminal operation requires minimal
host intervention.
• 40 MHz SPI Host Interface.
• MIL-STD-1760 option sets Busy bit in Status
Word response during initialization.
• World’s smallest MIL-STD-1553 terminal, QFN
package measures just 6mm x 6mm.
• Simple Monitor Terminal (SMT) Mode records
commands and data separately, with 16-bit or 48-
bit time tagging.
• Independent 16-bit time tag counters and clock
sources for RT and MT. The MT also has a 48-bit
time count option.
• 64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources.
48 - Pin Plastic 6mm x 6mm
Chip-Scale Package (QFN)
See Section 24.1 on page 202 for 48-Pin PQFP Configuration
DS6136 Rev. E
HOLT INTEGRATED CIRCUITS
www.holtic.com
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HI-6136
11.14. SMT Bus Monitor Interrupt Registers and Their Use................................................. 67
11.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011)............................................ 68
11.14.2. SMT Bus Monitor Pending Interrupt Register (0x0008).......................................... 68
11.14.3. SMT Bus Monitor Interrupt Output Enable Register (0x0015)................................ 68
12. REMOTE TERMINAL − OVERVIEW ............................................................... 70
13. REMOTE TERMINAL REGISTERS.................................................................. 71
13.1. Remote Terminal Configuration Register (0x0017) ................................................... 71
13.2. Remote Terminal Operational Status Register (0x0018) .......................................... 75
13.3. Remote Terminal Current Command Register (0x0002)............................................ 77
13.4. Remote Terminal Current Control Word Address Register (0x0003) ........................ 77
13.5. Remote Terminal Descriptor Table Base Address Register (0x0019)........................ 77
13.6. Remote Terminal MIL-STD-1553 Status Word Bits Register (0x001A)...................... 78
13.7. Remote Terminal Current Message Information Word Register (0x001B)................. 79
13.8. Remote Terminal Bus A Select Register (0x001C).................................................... 80
13.9. Remote Terminal Bus B Select Register (0x001D).................................................... 80
13.10. Remote Terminal Built-In Test (BIT) Word Register (0x001E).................................... 81
13.11. Remote Terminal Alternate Built-In Test (BIT) Word Register (0x001F)..................... 82
13.12. Remote Terminal Time Tag Counter Register (0x0049)............................................. 83
13.13. Remote Terminal Time Tag Utility Register (0x004A)................................................. 83
13.13.1. RT Time Tag Counter Loading ............................................................................... 83
13.13.2. RT Time Tag Count Match Interrupts ..................................................................... 83
13.14. Remote Terminal Interrupt Registers and Their Use.................................................. 84
13.14.1. Remote Terminal (RT) Interrupt Enable Register (0x0012).................................... 85
13.14.2. Remote Terminal (RT) Pending Interrupt Register (0x0009).................................. 85
13.14.3. Remote Terminal (RT) Interrupt Output Enable Register (0x0016)........................ 85
14. REMOTE TERMINAL CONFIGURATION AND OPERATION........................... 88
14.1. Command Responses............................................................................................... 88
14.1.1. RT to RT Commands. ............................................................................................ 90
14.2. Command Illegalization Table.................................................................................... 90
14.3. Temporary Receive Data Buffer................................................................................. 95
14.4. Descriptor Table......................................................................................................... 95
14.4.1. Receive Subaddress Control Word........................................................................ 98
14.4.2. Transmit Subaddress Control Word..................................................................... 101
14.4.3. Data Buffer Options for Mode Code Commands.................................................. 104
HOLT INTEGRATED CIRCUITS
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HI-6136
List of Tables
Table 1. Pin Descriptions.............................................................................................................. 14
Table 2. Host Interface Pins.......................................................................................................... 16
Table 3. Register Summary.......................................................................................................... 22
Table 4. Message Block in Circular Command Buffer for SMT Monitor using 16-bit Time Tag.... 50
Table 5. Message Block in Circular Command Buffer for SMT Monitor using 48-bit Time Tag.... 51
Table 6. Monitor Address List for SMT Mode................................................................................ 52
Table 7. SMT Message Filter Table.............................................................................................. 59
Table 8. Summary of Data Buffer Modes. ...................................................................................112
Table 9. Circular Buffer Mode 2 (Initialization factors based on message block size)................ 134
Table 10. Mode Code Command Summary............................................................................... 139
Table 11. Terminal Unlock Word Encoding................................................................................. 144
Table 12. Registers are not written using EEPROM data........................................................... 145
Table 13. READY delay times: from MR input pin rising edge to READY output pin rising edge.....
147
Table 14. RT Soft Reset Summary............................................................................................. 151
Table 15. SMT Soft Reset Summary.......................................................................................... 152
Table 16. Fast-Access SPI Commands for Lower Registers ..................................................... 169
Table 17. SPI Commands using Memory Address Pointer......................................................... 170
HOLT INTEGRATED CIRCUITS
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HI-6136.PDF ] | |
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