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FIN210AC の電気的特性と機能

FIN210ACのメーカーはFairchild Semiconductorです、この部品の機能は「10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz」です。


製品の詳細 ( Datasheet PDF )

部品番号
FIN210AC
部品説明
10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
メーカ
Fairchild Semiconductor
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Fairchild Semiconductor ロゴ 




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FIN210AC Datasheet, FIN210AC PDF,ピン配置, 機能
June 2009
FIN210AC
10-Bit Serializer / Deserializer Supporting Cameras and
Small Displays up to 48MHz
Features
Data & Control Bits
Frequency
Capability
Interface
µController Usage
Selectable Edge Rates
Standby Current
Core Voltage (VDDA/S)
I/O Voltage (VDDP)
ESD (I/O to GND)
Package
Ordering Information
10-bit
48MHz
Camera or LCD
Microcontroller, RGB, YUV
m68 & i86
Yes
<10µA
2.8 to 3.6V
1.65 to 3.6V
15kV
32-Terminal MLP (Preliminary)
42-Ball USS-BGA
FIN210ACMLX (Preliminary)
FIN210ACGFX
Description
The FIN210AC µSerDes™ is a low-power serializer /
deserializer optimized for use in cell phone displays and
camera paths. The device reduces a 10-bit data path to four
wires. For camera applications, an additional master clock
can be passed in the opposite direction of data flow. The
device utilizes Fairchild’s proprietary ultra-low power, low-
EMI technology.
Applications
ƒ Slider, Folder, & Clamshell Mobile Handsets
ƒ Printers
ƒ Security Cameras
Typical Application
www.DataSheet4U.com
Baseband
Related Resources
ƒ For samples and questions, please contact:
FIN210AC
Internal
Termination
Built-in voltage
translation
FIN210AC
Camera
Module
+ 2+
-
-
2
++
--
CTL™
Isolates interface
for signal integrity
Camera
Module
Up to 48MHz
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
Figure 1. Mobile Phone Example
www.fairchildsemi.com

1 Page





FIN210AC pdf, ピン配列
FIN210AC (Deserializer DIRI=0) Pin Descriptions
Pin Name
DIRI
XTERM
S0
Description
Control to determine serializer or deserializer configuration.
Control to determine if using internal or external termination
0 Deserializer
1 Serializer
0 Internal termination used
1 External termination required on CKSI & DSI
Signals used to define the edge rate of parallel I/O.
See Table 2 Deserializer (DIRI=0) Control Pin.
S1 Signals used to define the edge rate of parallel I/O.
See Table 2 Deserializer (DIRI=0) Control Pin.
PWS0
Configure CKP pulse width.
See Table 2 Deserializer (DIRI=0) Control Pin.
PWS1
Configure CKP pulse width.
See Table 2 Deserializer (DIRI=0) Control Pin.
/ENZ
DP[1:10]
CKP
DSI+
DSI-
CKSI+
CKSI-
CKSO+
CKSO-
CKREF
STROBE
/DIRO
VDDP
VDDS
VDDA
GND
N/C
High-Z or known state outputs during power down
See Table 5 Deserializer (DIRI=0) Control Pin.
LV-CMOS parallel data output. (N/C if not used)
LV-CMOS word clock output or Pixel clock output.
CTL Differential serial input data signals.
DSI+: Positive signal; DSI-: Negative signal.
CTL Differential deserializer input bit clock.
CKSI+: Positive signal; CKSI-: Negative signal.
CTL Differential serializer output bit clock.
CKSO+: Positive signal; CKSO-: Negative signal.
No connect unless in “clock pass-through” mode.
LV-CMOS clock input and PLL reference.
No connect unless in “clock pass-through” mode.
LV-CMOS strobe input for latching data into the serializer.
No connect unless in “clock pass-through” mode.
LV-CMOS Output. Inversion of DIRI in normal operation.
No connect if not used.
Power supply for parallel I/O. (All VDDP pins must be connected to VDDP)
Power supply for serial I/O.
Power supply for core.
All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 28, 29, GND PAD must be grounded.
No connect. BGA: G1, F2; MLP: 10, 11; (Do not connect to GND or VDD)
Note:
2. 0=GND; 1=VDDP
FIN210AC (Deserializer DIRI=0) Pin Configurations
123456
A DP[4]
DP[2]
XTRM
/ENZ
N/C CKREF
www.DataSBheet4DUP.[c6]om DP[5]
DP[1]
N/C STROBE /DIRO
C CKP N/C DP[3] N/C CKSO+ CKSO-
D N/C
DP[7]
VDDP
GND
DSI+
DSI-
E DP[8]
DP[9]
GND
VDDS
CKSI+
CKSI-
F DP[10]
N/C
N/C VDDA N/C
DIRI
DP[4] 1
DP[5] 2
DP[6] 3
VDDP 4
CKP 5
DP[7] 6
DP[8] 7
DP[9] 8
DESERIALIZER
GND PAD
24 CKSO+
23 CKSO-
22 DSI-
21 DSI+
20 CKSI-
19 CKSI+
18 DIRI
17 VDDS
G N/C
N/C
PWS1
PWS0
S1
S0
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
32-pin MLP, 5mm x 5mm, .5mm pitch (Top View)
(Center pad must be grounded)
Figure 3. FIN210AC (Deserializer DIRI=0) Pin Assignments (Top View)
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
3
www.fairchildsemi.com


3Pages


FIN210AC 電子部品, 半導体
Clock Pass-Through Mode
Clock pass-through mode allows a harmonic rich clock source to be sent to the serializer in a CTL format to reduce the
overall harmonic content of the phone, and can reduce the need for EMI filters. The Master Clock Pass through mode
performs a translation to the clock in the CTL link, and does not serialize this signal. The following describes how to enable
this functionality for an image sensor (See Figure 6).
Deserializer Configuration (DIRI=0)
1. Connect CKREF(BGA pin A6) to GROUND
2. Connect master clock to STROBE (BGA pin B5)
Serializer Configuration (DIRI=1)
1. CKSI passes master clock to CKP output (BGA pin C1)
CKREF and STROBE Signals
Please note that there is a setup and hold time between STROBE and data that must be met as seen on the electrical
characteristics section. The relationship between CKREF and STROBE can be synchronous or asynchronous depending on
what is available in the system. It is suggested that if the signals are synchronous and in normal operation that CKREF is tied
to STROBE as close to the chip as possible. If you are running an asynchronous or spread spectrum setup, please be aware
this may result on cycle jitter on the CKP signal. They cycle jitter does not effect the output data and clock relationship, the
display or end application should continue to work as normal.
PLL Note
Please note that the PLL ranges can overlap, power consumption can be reduced by selecting the operation in the lower end
of the higher speed PLL range.
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© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
6
www.fairchildsemi.com

6 Page

合計 : 17 ページ
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部品番号部品説明メーカ
FIN210AC

10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz

Fairchild Semiconductor
Fairchild Semiconductor

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