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ADA8282 の電気的特性と機能

ADA8282のメーカーはAnalog Devicesです、この部品の機能は「4-Channel LNA and PGA」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADA8282
部品説明 4-Channel LNA and PGA
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADA8282 Datasheet, ADA8282 PDF,ピン配置, 機能
Data Sheet
FEATURES
4 channels of low noise amplifiers (LNAs) followed by
programmable gain amplifiers (PGAs)
Minimum −3 dB bandwidth of 5 MHz
Typical –3 dB bandwidth of 42.3 MHz
Typical slew rate of 28 V/µs
Differential input and output
Gain of 18 dB to 36 dB in 6 dB steps
Selectable low noise and low power modes
Input referred noise of 4.5 nV/√Hz at 18.3 mW per channel
Input referred noise of 3.8 nV/√Hz at 26.5 mW per channel
Input referred noise of 3.6 nV/√Hz at 34.8 mW per channel
Input referred noise of 3.4 nV/√Hz at 54.8 mW per channel
Channel to channel gain matching of ±0.25 dB
Absolute gain error of ±0.5 dB
SPI programmable
Power-down mode (SPI selectable)
3.1 V p-p differential output swing when using a 3.3 V supply
32-lead, 5 mm × 5 mm LFCSP package
Specified from −40°C to +125°C
Qualified for automotive applications
APPLICATIONS
Automotive radar
Adaptive cruise control
Collision avoidance
Blind spot detection
Self parking
Electronic bumpers
GENERAL DESCRIPTION
The ADA8282 is designed for applications that require low cost,
low power, compact size, and flexibility. The ADA8282 has four
parallel channels, eachincluding anLNA and a PGA. The LNA
and PGA combine to form a signal chainthat features a gain range
of 18 dB to 36 dB in 6 dB increments with a guaranteed
minimum bandwidth of 5 MHz.
Using the highest power settings, the combinedinput referred
voltage noise of the combined LNA and PGA channel is
3.4 nV/√Hz at maximum gain.
Radar Receive Path AFE:
4-Channel LNA and PGA
ADA8282
FUNCTIONAL BLOCK DIAGRAM
+INA
–INA
ADA8282
3nV√Hz LNA
PGA
+24dB –6dB TO +12dB
+INB
–INB
3nV√Hz LNA
PGA
+24dB –6dB TO +12dB
+INC
–INC
3nV√Hz LNA
PGA
+24dB –6dB TO +12dB
+IND
–IND
3nV√Hz LNA
PGA
+24dB –6dB TO +12dB
POWER GAIN
MODE SELECT
+OUTA
–OUTA
+OUTB
–OUTB
+OUTC
–OUTC
+OUTD
–OUTD
SPI
CS SCLK SDI SDO VIO AVDD RESET
Figure 1.
The ADA8282 can be configured in four power modes that
trade off power andnoise performance to optimize the overall
performance according to the end application.
Fabricated in an advanced complementary metal-oxide
semiconductor (CMOS) process, the ADA8282 is available in a
5 mm × 5 mm, RoHS-compliant, 32-leadLFCSP. It is specified
over the automotive temperature range of −40°C to +125°C.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility isassumedby AnalogDevicesforits use,norforany infringements of patents orother
rights of thirdparties thatmay resultfrom its use.Specificationssubjecttochangewithoutnotice.No
license is granted by implicationor otherwise underany patentorpatentrights of AnalogDevices .
Trademarks andregistered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





ADA8282 pdf, ピン配列
Data Sheet
ADA8282
SPECIFICATIONS
AVDD = 3.3 V, LNA + PGA gain = 36 dB (LNA gain = 24 dB, PGA gain = 12 dB), TA = −40°C to +125°C, PGA_BIAS_SEL = b’10,
LNA_BIAS_SEL= b’10, unless otherwise noted.
Table 1.
Parameter
ANALOG CHANNEL CHARACTERISTICS
Gain
Gain Range
Gain Error
−3 dB Bandwidth
Channel to Channel Gain Matching
Channel to Channel Phase Matching1
Slew Rate
Input Referred Noise
Output Referred Noise
Offset Voltage
Referred to Input
Referred to Output
SPI Offset Adjustment Resolution
(Relative to Input)
SPI Offset Adjustment Range (Relative
to Input)
Harmonic Distortion
Second Harmonic (HD2)
Third Harmonic (HD3)
Intermodulation Distortion
Common-Mode Rejection Ratio (CMRR)
Crosstalk
Test Conditions/Comments
VOUT = 100 mV p-p, gain = 36 dB
PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10
PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11
Frequencies up to 5 MHz
Frequencies up to 5 MHz
Gain = 36 dB at 2 MHz
PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10
PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11
50 Ω impedance used for voltage to power
conversion
Gain = 18 dB
Gain = 24 dB
Gain = 30 dB
Gain = 36 dB
Gain = 36 dB
Gain = 36 dB
LNA_BIAS_SEL = b’00
LNA_BIAS_SEL = b’01
LNA_BIAS_SEL = b’10
LNA_BIAS_SEL = b’11
LNA_BIAS_SEL = b’00
LNA_BIAS_SEL = b’01
LNA_BIAS_SEL = b’10
LNA_BIAS_SEL = b’11
VOUT = 2 V p-p, fIN = 100 kHz
VOUT = 100 mV p-p, fIN = 2 MHz
VOUT = 2 V p-p, fIN = 100 kHz
VOUT = 100 mV p-p, fIN = 2 MHz
VOUT = 2 V p-p, fIN1 = 100 kHz, fIN2 = 150 kHz
VOUT = 100 mV p-p, fIN1 = 2 MHz, fIN2 = 2.1 MHz
Min
5
5
5
5
Typ Max Unit
18/24/30/36
18
±0.5
dB
dB
dB
20.5 MHz
34.2 MHz
42.3 MHz
52.3 MHz
0.1 ±0.25 dB
0.1 ±1 Degrees
28 V/μs
4.5
3.8
3.6
3.4
−156
36
61
115
218
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
dBm/Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
±0.8 ±3 mV
±50 ±200 mV
113 μV
186 μV
250 μV
440 μV
±4 mV
±6 mV
±8 mV
±14 mV
−70
−85
−85
−95
−72
−83
−80
−105
dBc
dBc
dBc
dBc
dBc
dBc
dB
dBc
Rev. 0 | Page 3 of 21


3Pages


ADA8282 電子部品, 半導体
ADA8282
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
+INA 1
–INA 2
+INB 3
–INB 4
+INC 5
–INC 6
+IND 7
–IND 8
ADA8282
TOP VIEW
(Not to Scale)
24 +OUTA
23 –OUTA
22 +OUTB
21 –OUTB
20 +OUTC
19 –OUTC
18 +OUTD
17 –OUTD
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. TIE THE EXPOSED PAD ON THE BOTTOM SIDE OF THE
PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
0 EPAD Exposed Pad. Tie the exposed pad on the bottom side of the package to the analog/digital ground plane.
1 +INA Positive LNA Analog Input for Channel A.
2 −INA Negative LNA Analog Input for Channel A.
3 +INB Positive LNA Analog Input for Channel B.
4 −INB Negative LNA Analog Input for Channel B.
5 +INC Positive LNA Analog Input for Channel C.
6 −INC Negative LNA Analog Input for Channel C.
7 +IND Positive LNA Analog Input for Channel D.
8 −IND Negative LNA Analog Input for Channel D.
9
AVDD
3.3 V Analog Supply.
10 NIC
No Internal Connection. Leave this pin floating.
11 NIC
No Internal Connection. Leave this pin floating.
12 NIC
No Internal Connection. Leave this pin floating.
13 NIC
No Internal Connection. Leave this pin floating.
14 NIC
No Internal Connection. Leave this pin floating.
15 NIC
No Internal Connection. Leave this pin floating.
16 AVDD
3.3 V Analog Supply.
17
−OUTD
Negative Analog Output for Channel D.
18
+OUTD
Positive Analog Output for Channel D.
19
−OUTC
Negative Analog Output for Channel C.
20
+OUTC
Positive Analog Output for Channel C.
21
−OUTB
Negative Analog Output for Channel B.
22
+OUTB
Positive Analog Output for Channel B.
23
−OUTA
Negative Analog Output for Channel A.
24
+OUTA
Positive Analog Output for Channel A.
25 AVDD
3.3 V Analog Supply.
26 VIO
Digital Level Select for SPI and RESET. This pin can accept 1.8 V to 3.3 V.
27 RESET Reset Input. RESET overrides the SPI and powers down the device and returns all settings back to default. RESET is
pulled to ground by default. A logic high triggers the reset.
28 SCLK
Serial Clock.
29 CS
Chip Select Bar.
30 SDI
Serial Data Input.
31 SDO
Serial Data Output.
32 AVDD
3.3 V Analog Supply.
Rev. 0 | Page 6 of 21

6 Page



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部品番号部品説明メーカ
ADA8282

4-Channel LNA and PGA

Analog Devices
Analog Devices


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