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GS2961 の電気的特性と機能

GS2961のメーカーはGennumです、この部品の機能は「Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS2961
部品説明 Receiver
メーカ Gennum
ロゴ Gennum ロゴ 




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GS2961 Datasheet, GS2961 PDF,ピン配置, 機能
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
complete with SMPTE Video Processing
Key Features
• Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 425M (Level A and Level B), SMPTE
424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 150m at 2.97Gb/s
Š 250m at 1.485Gb/s
Š 480m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Ancillary data extraction
• Optional conversion from SMPTE 425M Level B to
Level A for 1080p 50/60 4:2:2 10-bit
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• -20ºC to +85ºC operating temperature range
• Low power operation (typically 515mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and ROHS compliant
Errata
Refer to Errata document entitled GS2960/GS2961 Errata
for this device (document number 53117).
Applications
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
3G-SDI
GS2961
10-bit
HV F/PCLK
HV F/PCLK
10-bit
GS2962
GS2962
HD-SDI
Link A
HD-SDI
Link B
HD-SDI
Link A
HD-SDI
Link B
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Deserializer
GS2961
10-bit
HV F/PCLK
FIFO
WR
HD-SDI
Deserializer
GS2961
10-bit
HV F/PCLK
FIFO
WR
10-bit
HV F/PCLK
10-bit
GS2962
3G-SDI
GS4910
HVF
X TAL
Description
The GS2961 is a multi-rate SDI integrated Receiver which
includes complete SMPTE processing, as per SMPTE 425M,
292M and SMPTE 259M-C. The SMPTE processing features
can be bypassed to support signals with other coding
schemes.
The GS2961 integrates Gennum's adaptive cable equalizer
technology, achieving unprecedented cable lengths and
jitter tolerance. It features DC restoration to compensate for
the DC content of SMPTE pathological signals.
The device features an Integrated Reclocker with an
internal VCO and a wide Input Jitter Tolerance (IJT) of
0.7UI.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
www.gennum.com
1 of 104

1 Page





GS2961 pdf, ピン配列
Revision History
Version ECR PCN
2 153143 53865
1
152698
0
151888
C
151697
B
151504
A
151219
Date
November 2009
October 2009
June 2009
April 2009
March 2009
February 2009
Changes and/or Modifications
Added reference to GS2960/GS2961
Errata (document number 53117).
Converted to Data Sheet.
Updated Power numbers in Table 2-3:
DC Electrical Characteristics.
Conversion to Preliminary Data Sheet.
Corrections to Timing Diagrams in
Figure 4-5, Figure 4-6 and Figure 4-7.
Clarification to Section 4.18.8. Updates
to all sections.
Updated equalized cable lengths and
power numbers in Key Features, Table
2-4: AC Electrical Characteristics and
Section 4.3.1.
Changed pin H3 from ‘RSV’ to
CORE_GND’ in 1.1 Pin Assignment, 1.2
Pin Descriptions and 5.3 Typical
Application Circuit.
New Document.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
3 of 104


3Pages


GS2961 電子部品, 半導体
7.3 Marking Diagram ......................................................................................................................... 102
7.4 Solder Reflow Profiles ................................................................................................................ 103
7.5 Ordering Information ................................................................................................................. 103
List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 23
Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 23
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength......... 24
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 24
Figure 3-5: VBG .............................................................................................................................................. 25
Figure 3-6: LB_CONT .................................................................................................................................... 25
Figure 3-7: Loop Filter .................................................................................................................................. 25
Figure 3-8: SDO/SDO .................................................................................................................................... 26
Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 26
Figure 4-1: Level A Mapping ...................................................................................................................... 28
Figure 4-2: Level B Mapping ...................................................................................................................... 28
Figure 4-3: GS2961 Integrated EQ Block Diagram ............................................................................. 30
Figure 4-4: 27MHz Clock Sources ............................................................................................................ 32
Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 35
Figure 4-6: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 36
Figure 4-7: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 37
Figure 4-8: DDR Video Interface .............................................................................................................. 40
Figure 4-9: Delay Adjustment Ranges .................................................................................................... 41
Figure 4-10: Switch Line Locking on a Non-Standard Switch Line ............................................... 43
Figure 4-11: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 47
Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 47
Figure 4-13: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 48
Figure 4-14: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 48
Figure 4-15: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 48
Figure 4-16: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 48
Figure 4-17: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 48
Figure 4-18: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 50
Figure 4-19: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 51
Figure 4-20: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 52
Figure 4-21: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 52
Figure 4-22: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 53
Figure 4-23: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 54
Figure 4-24: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 54
Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 55
Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 55
Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 56
Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 56
Figure 4-29: Y/1ANC and C/2ANC Signal Timing .............................................................................. 66
Figure 4-30: Ancillary Data Extraction - Step A .................................................................................. 73
Figure 4-31: Ancillary Data Extraction - Step B ................................................................................... 74
Figure 4-32: Ancillary Data Extraction - Step C .................................................................................. 75
Figure 4-33: Ancillary Data Extraction - Step D .................................................................................. 76
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
6 of 104

6 Page



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共有リンク

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