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PDF SI5350C-B Data sheet ( Hoja de datos )
| Número de pieza | SI5350C-B | |
| Descripción | FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR + PLL | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si5350C-B
FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS
CLOCK GENERATOR + PLL
Features
www.silabs.com/custom-timing
Operates from a low-cost, fixed
Generates up to 8 non-integer-related frequency crystal: 25 or 27 MHz
frequencies from 2.5 kHz to 200 MHz Separate voltage supply pins provide
Exact frequency synthesis at each
level translation:
output (0 ppm error)
Core VDD: 1.8V, 2.5 V or 3.3 V
Glitchless frequency changes
Output VDDO: 1.8 V, 2.5 V, or 3.3 V
Low output period jitter: < 70 ps pp, typ Excellent PSRR eliminates external
Configurable Spread Spectrum
power supply filtering
selectable at each output
Very low power consumption (25 mA
User-configurable control pins:
core, typ)
Output Enable (OEB_0/1/2)
Available in 2 packages types:
Power Down (PDN)
10-MSOP: 3 outputs
Frequency Select (FS_0/1)
20-QFN (4x4 mm): 8 outputs
Spread Spectrum Enable (SSEN)
Loss of Lock Status (LOLB)
Supports static phase offset
PCIE Gen 1 compliant
Supports HCSL compatible swing
Rise/fall time control
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld instrumentation
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
The Si5350C generates free-running and/or synchronized clocks selectable on each
of its outputs. A dual PLL + high resolution MultiSynthTM fractional divider
architecture enables this user-definable custom timing device to generate any of the
specified output frequencies at any of its outputs. This allows the Si5350C to replace
a combination of crystals, crystal oscillators, and synchronized clocks (PLL). Custom
pin-controlled Si5350C devices can be requested using the ClockBuilder web-based
part number utility (www.silabs.com/ClockBuilder).
10-MSOP
20-QFN
Ordering Information:
See Page 18
Functional Block Diagram
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si5350C-B
1 page  
Si5350C-B
Table 4. AC Characteristics
(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Power-Up Time
Powerup Time, PLL Bypass
Mode
Output Enable Time
Output Frequency Transition
Time
Spread Spectrum Frequency
Deviation
Spread Spectrum
Modulation Rate
Symbol
TRDY
TBYP
TOE
Test Condition
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
From OEB assertion to valid
clock output, CL = 5 pF, fCLKn
> 1 MHz
TFREQ
SSDEV
fCLKn > 1 MHz
Down Spread
Selectable in 0.1% steps
SSMOD_C
Min
—
—
—
—
–0.1
30
Typ
2
0.5
—
—
—
31.5
Max
10
1
10
10
–2.5
33
Unit
ms
ms
µs
µs
%
kHz
Table 5. Input Characteristics
(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Crystal Frequency
fXTAL
25 — 27 MHz
P0-P3 Input Low Voltage
VIL_P0-3
–0.1
— 0.3 x VDD V
P0-P3 Input High Voltage
VIH_P0-3
VDD = 2.5 V or 3.3 V 0.7 x VDD
VDD = 1.8 V
0.8 x VDD
—
—
3.60 V
3.60 V
CLKIN Frequency Range
fCLKIN
10 — 100 MHz
CLKIN Input Low Voltage
VIL_CLKIN
–0.1
— 0.3 x VDD V
CLKIN Input High Voltage
VIH_CLKIN
0.7 x VDD
—
3.60 V
Rev. 1.0
5
5 Page 
Si5350C-B
4. Configuring the Si5350C
The Si5350C is a factory-programmed custom clock generator that is user definable with a simple to use web-
based utility (www.silabs.com/ClockBuilder). The ClockBuilder utility provides a simple graphical interface that
allows the user to enter input and output frequencies along with other custom features as described in the following
sections. All synthesis calculations are automatically performed by ClockBuilder to ensure an optimum
configuration. A unique part number is assigned to each custom configuration.
4.1. Crystal Inputs (XA, XB)
The Si5350C uses an optional fixed-frequency non-pullable standard AT-cut crystal as a reference to generate
free-running output clocks. Note that a XTAL is not required for generating synchronous clocks that are locked to
CLKIN.
4.1.1. Crystal Frequency
The Si5350C can operate using either a 25 MHz or a 27 MHz crystal.
4.1.2. Internal XTAL Load Capacitors
Internal load capacitors are provided to eliminate the need for external components when connecting a XTAL to the
Si5350C. The total internal XTAL load capacitance (CL) can be selected to be 0, 6, 8 or 10 pF. XTALs with alternate
load capacitance requirements are supported using additional external load capacitance 2 pF (e.g., by using 4
pF capacitors on XA and XB) as shown in Figure 5.
XA
XB
Optional additional
external load
capacitance
(< 2 pF)
Optional internal
load capacitance
0, 6, 8,10 pF
Figure 5. External XTAL with Optional Load Capacitors
4.2. External Clock Input Pin (CLKIN)
The external clock input is used as a reference for generating synchronous clocks. The input frequency can be
specified from 10 to 100 MHz including fractional frequencies (e.g., 74.25 MHz x 1000/1001). The ClockBuilder
utility automatically determines the exact synthesis ratio to guarantee an output frequency with 0 ppm error with
respect to its reference.
4.3. Output Clocks (CLK0–CLK7)
The Si5350C is orderable as a 3-output (10-MSOP) or 8-output (20-QFN) clock generator. Output clocks CLK0 to
CLK5 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the optional frequency
select pins (FS0/1). See “4.4.3. Frequency Select (FS_0, FS_1)” for more details on the operation of the frequency
select pins. Each output clock can select its reference for either of the PLLs.
4.3.1. Output Clock Frequency
Outputs can be configured at any frequency from 2.5 kHz up to 200 MHz. However, only two unique frequencies
above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
(CLKS4-7).
Rev. 1.0
11
11 Page | ||
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