PDF SI5327 Data sheet ( Hoja de datos )

Número de pieza	SI5327
Descripción	ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Fabricantes	Silicon Laboratories
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Si5327 ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features  Generates any frequency from 2 kHz  Dual clock inputs with manually to 808 MHz from an input frequency controlled hitless switching of 2 kHz to 710 MHz  Free run and VCO freeze modes  Ultra-low jitter clock outputs with jitter  Support for ITU G.709 and custom generation as low as 0.5 ps rms FEC ratios (255/238, 255/237, (12 kHz–20 MHz) 255/236)  Integrated loop filter with selectable  LOL and LOS alarm outputs loop bandwidth (4 to 525 Hz)  I2C or SPI programmable  Meets OC-192 GR-253-CORE jitter  Single 1.8, 2.5, 3.3 V supply specifications  Small size: 6 x 6 mm 36-lead QFN  Pb-free, ROHS compliant Applications  Dual clock outputs with  Synchronous Ethernet programmable signal format  Optical modules (LVPECL, LVDS, CML, CMOS)  Wireless repeaters/  SONET/SDH OC-48/OC-192/STM- wireless backhaul 16/STM-64 line cards  Data converter clocking  ITU G.709 and custom FEC line  xDSL cards  PDH clock synthesis  GbE/10GbE, 1/2/4/8/10G Fibre  Test and measurement Channel line cards  Broadcast video Description The Si5327 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5327 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 808 MHz. The two outputs are divided down separately from a common source. The Si5327 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5327 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5327 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5327 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Ordering Information: See page 54. Pin Assignments 36 35 34 33 32 31 30 29 28 RST 1 27 SDI NC 2 26 A2_SS INT_LOS1 3 25 A1 LOS2 4 VDD 5 XA 6 GND Pad 24 A0 23 SDA_SDO 22 SCL XB 7 21 CKSEL GND 8 20 NC NC 9 19 NC 10 11 12 13 14 15 16 17 18 Rev. 1.0 1/13 Copyright © 2013 by Silicon Laboratories Si5327 1 page Si5327 Table 2. DC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Supply Current1 Symbol IDD Test Condition LVPECL Format 622.08 MHz Out Both CKOUTs Enabled LVPECL Format 622.08 MHz Out 1 CKOUT Enabled CMOS Format 19.44 MHz Out Both CKOUTs Enabled CMOS Format 19.44 MHz Out 1 CKOUT Enabled Disable Mode Min — — — — — Typ 251 217 204 194 165 Max Unit 279 mA 243 mA 234 mA 220 mA — mA CKINn Input Pins2 Input Common Mode Voltage (Input Threshold Voltage) VICM 1.8 V ± 5% 2.5 V ± 10% 0.9 — 1.4 V 1 — 1.7 V 3.3 V ± 10% 1.1 — 1.95 V Input Resistance CKNRIN Single-ended 20 40 60 k Single-Ended Input Voltage Swing (See Absolute Specs) Differential Input Voltage Swing (See Absolute Specs) VISE VID fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. 0.2 0.25 0.2 0.25 — — — — — VPP — VPP — VPP — VPP Notes: 1. Current draw is independent of supply voltage. 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. Rev. 1.0 5 5 Page Si5327 Table 3. AC Specifications (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min PLL Performance (fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 40 MHz) Lock Time2 tLOCKMP Start of ICAL to of LOL — Settle Time2 tSETTLE Start of ICAL to FOUT within 5 ppm of final value — Output Clock Phase Change Closed Loop Jitter Peaking Jitter Tolerance tP_STEP JPK JTOL After clock switch f3  128 kHz — — Jitter Frequency Loop 5000/BW Bandwidth Phase Noise fout = 622.08 MHz 100 Hz Offset 1 kHz Offset — — Typ 1.9 5.5 200 0.05 — –80 –110 Max Unit 3s 6.5 s — ps 0.1 dB — ns pk-pk — dBc/Hz — dBc/Hz CKOPN 10 kHz Offset 100 kHz Offset — –113 — dBc/Hz — –117 — dBc/Hz 1 MHz Offset — –125 — dBc/Hz Subharmonic Noise SPSUBH Phase Noise @ 100 kHz — –80 — Offset dBc Spurious Noise SPSPUR Max spur @ n x F3 — –65 — (n  1, n x F3 < 100 MHz) dBc Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan. Please visit the Silicon Labs Technical Support web page at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. Rev. 1.0 11 11 Page

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