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74LVC02AのメーカーはON Semiconductorです、この部品の機能は「Low-Voltage CMOS Quad 2-Input NOR Gate」です。 |
部品番号 | 74LVC02A |
| |
部品説明 | Low-Voltage CMOS Quad 2-Input NOR Gate | ||
メーカ | ON Semiconductor | ||
ロゴ | |||
このページの下部にプレビューと74LVC02Aダウンロード(pdfファイル)リンクがあります。 Total 8 pages
74LVC02A
Low-Voltage CMOS Quad
2-Input NOR Gate
With 5 V−Tolerant Inputs
The 74LVC02A is a high performance, quad 2−input NOR gate
operating from a 1.2 to 3.6 V supply. High impedance TTL compatible
inputs significantly reduce current loading to input drivers while TTL
compatible outputs offer improved switching noise performance. A VI
specification of 5.5 V allows 74LVC02A inputs to be safely driven
from 5 V devices.
Current drive capability is 24 mA at the outputs.
Features
• Designed for 1.2 V to 3.6 V VCC Operation
• 5 V Tolerant Inputs − Interface Capability With 5 V TTL Logic
• 24 mA Output Sink and Source Capability
• Near Zero Static Supply Current (10 mA) Substantially Reduces
System Power Requirements
• ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
2
A0
3
B0
5
A1
6
B1
11
A2
12
B2
8
A3
9
B3
1
O0
4
O1
13
O2
10
O3
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 0
1
www.onsemi.com
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
VCC O2 B2 A2 O3 B3 A3
14 13 12 11 10 9 8
1234567
O0 A0 B0 O1 A1 B1 GND
MARKING DIAGRAMS
14
LVC02AG
AWLYWW
1
SOIC−14 NB
14
LVC
02A
ALYWG
G
1
TSSOP−14
A
WL, L
Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
74LVC02A/D
1 Page 74LVC02A
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC DC Supply Voltage
VI DC Input Voltage
VO DC Output Voltage
−0.5 to +6.5
−0.5 ≤ VI ≤ +6.5
−0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State
(Note 1)
V
V
V
IIK DC Input Diode Current
IOK DC Output Diode Current
IO
ICC
IGND
TSTG
TL
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for
10 Seconds
−50
−50
+50
±50
±100
±100
−65 to +150
TL = 260
VI < GND
VO < GND
VO > VCC
mA
mA
mA
mA
mA
mA
°C
°C
TJ Junction Temperature Under Bias
qJA Thermal Resistance (Note 2)
TJ = 135
SOIC = 85
TSSOP = 100
°C
°C/W
MSL
Moisture Sensitivity
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Typ Max Units
VCC Supply Voltage
Operating
Functional
V
1.65 3.6
1.2 3.6
VI Input Voltage
VO Output Voltage
HIGH or LOW State
3−State
0 5.5 V
V
0 VCC
0 5.5
IOH HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
mA
−24
−12
IOL LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
mA
24
12
TA Operating Free−Air Temperature
−40
+125
°C
Dt/DV
Input Transition Rise or Fall Rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
ns/V
0 20
0 10
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
3
3Pages 74LVC02A
An, Bn
On
Vmi
tPHL
Vmo
Vmi
tPLH
Vmo
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
0V
VOH
VOL
Symbol
Vmi
Vmo
3.3 V + 0.3 V
1.5 V
1.5 V
Vcc
2.7 V
1.5 V
1.5 V
VCC < 2.7 V
Vcc/2
Vcc/2
Figure 2. AC Waveforms
PULSE
GENERATOR
VCC
VI VO
DUT
RT CL RL
CL includes jig and probe capacitance
RT = ZOUT of pulse generator (typically 50 W)
Supply Voltage
VCC (V)
1.2
1.65 − 1.95
2.3 − 2.7
2.7
3 − 3.6
Input
VI tr, tf
VCC ≤ 2 ns
VCC
VCC
2.7 V
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
2.7 V ≤ 2.5 ns
Load
CL
30 pF
RL
1 kW
30 pF
1 kW
30 pF
500 W
50 pF
500 W
50 pF
500 W
Figure 3. Test Circuit
ORDERING INFORMATION
Device
Package
Shipping†
74LVC02ADR2G
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
74LVC02ADTR2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
6
6 Page | |||
ページ | 合計 : 8 ページ | ||
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部品番号 | 部品説明 | メーカ |
74LVC02 | Quad 2-input NOR gate | Philips |
74LVC02A | Low-Voltage CMOS Quad 2-Input NOR Gate | ON Semiconductor |