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GS1671A の電気的特性と機能

GS1671AのメーカーはSemtechです、この部品の機能は「HD/SD SDI Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS1671A
部品説明 HD/SD SDI Receiver
メーカ Semtech
ロゴ Semtech ロゴ 




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GS1671A Datasheet, GS1671A PDF,ピン配置, 機能
GS1671A
HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with
SMPTE Audio and Video Processing
Key Features
• Operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 230m at 1.485Gb/s
Š 440m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Integrated audio de-embedder for 8 channels of 48kHz
audio
• Integrated audio clock generator
• Ancillary data extraction
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• Wide temperature range of -40ºC to +85ºC
• Low power operation (typically 480mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Application: 1080p30 or 720p60 Monitor
HD-SDI
AES - OUT
GS1671A
AUDIO 1/2
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
Audio Clocks
Audio
Selector
10-bit
HV F/PCLK
Video
Processor
C TR L/TIMECODE
DAC
Speakers
DAC
Display
Application: Multi-format Downconverter
10-bit SD Bypass
Memory
SD/HD-SDI
GS1671A
10-bit
HV F/PCLK
Video
Downconverter &
Aspect Ratio
Conversion
Analog
Sync
Sync
Seperator
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
Audio
Processing
& Delay
GS4901
Audio Clocks
HV F/PCLK
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
10-bit
HD/SD
Serializer
(GS1672)
HD/SD-SDI
Application: Multi-input Video Monitoring System
HD-SDI
Input 1
HD-SDI
Input 2
GS1671A
10-bit
HV F/PCLK
GS1671A
10-bit
HV F/PCLK
Video
Memory
Video
Formatter
H V/DE/PCLK
DVI/
VGA DAC
Video
Output
HD-SDI
Input n
GS1671A
10-bit
HV F/PCLK
Analog
Sync
Sync
Seperator
AES BUS
GS4911
Audio
Select
HV F/PCLK
Audio Clocks
On Screen
Display
Generator
Audio
Processor
AE S OUT 1/2
AE S OUT 3/4
AE S OUT 5/6
AE S OUT 7/8
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
www.semtech.com
1 of 136

1 Page





GS1671A pdf, ピン配列
Functional Block Diagram
VBG
LB_CONT
LF
SDI
SDI
AGC+
AGC-
SDO
SDO
Crystal
Buffer/
Oscillator
GSPI and
JTAG Controller
Host
Interface
NGEN
EQ
Buffer
Reclocker
with
Integrated
VCO
Serial
to
Parallel
Converter
Descramble,
Word Align,
Rate Detect
Flywheel
Video
Standard
Detect
TRS
Detect
Timing
Extraction
Audio
De-Embedder,
Audio Clock
Generation
ANC/
Checksum
/352M
Extraction
Illegal code
remap,
TRS/
Line Number/
CRS
Insertion,
EDH Packet
Insertion
Mux
Output Mux/
Demux
Buffer
Mux
DVB-ASI
Decoder
I/O Control
PCLK
DOUT[19:0]
LOCKED
GS1671A Functional Block Diagram
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
3 of 136


3Pages


GS1671A 電子部品, 半導体
List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 23
Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 23
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 24
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 24
Figure 3-5: VBG .............................................................................................................................................. 24
Figure 3-6: LB_CONT .................................................................................................................................... 25
Figure 3-7: Loop Filter .................................................................................................................................. 25
Figure 3-8: SDO/SDO .................................................................................................................................... 25
Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 25
Figure 4-1: GS1671A Integrated EQ Block Diagram .......................................................................... 28
Figure 4-2: 27MHz Clock Sources ............................................................................................................ 30
Figure 4-3: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 34
Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 35
Figure 4-5: Switch Line Locking on a Non-Standard Switch Line ................................................. 39
Figure 4-6: H:V:F Output Timing - HDTV 20-bit Mode ..................................................................... 43
Figure 4-7: H:V:F Output Timing - HDTV 10-bit Mode ..................................................................... 43
Figure 4-8: H:V:F Output Timing - HD 20-bit Output Mode ............................................................ 43
Figure 4-9: H:V:F Output Timing - HD 10-bit Output Mode ............................................................ 44
Figure 4-10: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 44
Figure 4-11: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 44
Figure 4-12: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 46
Figure 4-13: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 46
Figure 4-14: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 47
Figure 4-15: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 47
Figure 4-16: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 48
Figure 4-17: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 49
Figure 4-18: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 49
Figure 4-19: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 50
Figure 4-20: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 50
Figure 4-21: 2K Feature Enhancement ................................................................................................... 53
Figure 4-22: Y/1ANC and C/2ANC Signal Timing .............................................................................. 60
Figure 4-23: Ancillary Data Extraction - Step A .................................................................................. 66
Figure 4-24: Ancillary Data Extraction - Step B ................................................................................... 67
Figure 4-25: Ancillary Data Extraction - Step C .................................................................................. 67
Figure 4-26: Ancillary Data Extraction - Step D .................................................................................. 68
Figure 4-27: ACLK to Data Signal Output Timing ............................................................................... 70
Figure 4-28: I2S Audio Output Format .................................................................................................... 71
Figure 4-29: AES/EBU Audio Output Format ....................................................................................... 71
Figure 4-30: Serial Audio, Left Justified, MSB First ............................................................................. 72
Figure 4-31: Serial Audio, Left Justified, LSB First .............................................................................. 72
Figure 4-32: Serial Audio, Right Justified, MSB First .......................................................................... 72
Figure 4-33: Serial Audio, Right Justified, LSB First ........................................................................... 72
Figure 4-34: AES/EBU Audio Output to Bit Clock Timing ................................................................ 72
Figure 4-35: ECC 24-bit Array and Examples ...................................................................................... 75
Figure 4-36: Sample Distribution Over Five Video Frames (525-line Systems) ........................ 76
Figure 4-37: Audio Buffer After Initial 26 Sample Write .................................................................. 77
Figure 4-38: Audio Buffer Pointer Boundary Checking .................................................................... 77
Figure 4-39: GSPI Application Interface Connection ........................................................................ 83
Figure 4-40: Command Word Format ..................................................................................................... 83
Figure 4-41: Data Word Format ................................................................................................................ 84
Figure 4-42: Write Mode .............................................................................................................................. 85
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
6 of 136

6 Page



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部品番号部品説明メーカ
GS1671A

HD/SD SDI Receiver

Semtech
Semtech


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