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GS1661A の電気的特性と機能

GS1661AのメーカーはSemtechです、この部品の機能は「HD/SD SDI Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS1661A
部品説明 HD/SD SDI Receiver
メーカ Semtech
ロゴ Semtech ロゴ 




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GS1661A Datasheet, GS1661A PDF,ピン配置, 機能
GS1661A
HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with
SMPTE Video Processing
Key Features
• Operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 230m at 1.485Gb/s
Š 440m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Ancillary data extraction
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• Wide temperature range of -40ºC to +85ºC
• Low power operation (typically 460mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
HD-SDI
Link A
HD-SDI
Link B
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Deserializer
GS1661A
10-bit
HV F/PCLK
FIFO
WR
HD-SDI
Deserializer
GS1661A
10-bit
HV F/PCLK
FIFO
WR
10-bit
HV F/PCLK
10-bit
GS2962
3G-SDI
GS4910
HVF
X TAL
Description
The GS1661A is a multi-rate SDI integrated Receiver which
includes complete SMPTE processing, as per SMPTE 292M
and SMPTE 259M-C. The SMPTE processing features can be
bypassed to support signals with other coding schemes.
The GS1661A integrates Gennum's adaptive cable
equalizer technology, achieving unprecedented cable
lengths and jitter tolerance. It features DC restoration to
compensate for the DC content of SMPTE pathological
signals.
The device features an Integrated Reclocker with an
internal VCO and a wide Input Jitter Tolerance (IJT) of
0.7UI.
A serial digital loop-through output is provided, which can
be configured to output either reclocked or non-reclocked
serial digital data. The serial digital output can be
connected to an external cable driver.
The device operates in one of four basic modes: SMPTE
mode, DVB-ASI mode, Data-Through mode or Standby
mode.
In SMPTE mode (the default operating mode), the GS1661A
performs full SMPTE processing, and features a number of
data integrity checks and measurement capabilities.
The device also supports ancillary data extraction, and can
provide entire ancillary data packets through
host-accessible registers. It also provides a variety of other
packet detection and error handling features. All of these
processing features are optional, and may be individually
enabled or disabled through register programming.
In DVB-ASI mode, sync word detection, alignment and
8b/10b decoding is applied to the received data stream.
In Data-Through mode all forms of SMPTE and DVB-ASI
processing are disabled, and the device can be used as a
simple serial to parallel converter.
The device can also operate in a lower power Standby
mode. In this mode, no signal processing is carried out and
the parallel output is held static.
GS1661A HD/SD SDI Receiver
Data Sheet
54387 - 2
September 2012
www.semtech.com
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GS1661A pdf, ピン配列
Contents
Key Features ........................................................................................................................................................1
Applications ......................................................................................................................................................... 1
Description ........................................................................................................................................................... 1
Functional Block Diagram ..............................................................................................................................2
1. Pin Out...............................................................................................................................................................7
1.1 Pin Assignment ..................................................................................................................................7
1.2 Pin Descriptions ................................................................................................................................7
2. Electrical Characteristics ......................................................................................................................... 14
2.1 Absolute Maximum Ratings ....................................................................................................... 14
2.2 Recommended Operating Conditions .................................................................................... 14
2.3 DC Electrical Characteristics ..................................................................................................... 15
2.4 AC Electrical Characteristics ..................................................................................................... 16
3. Input/Output Circuits ............................................................................................................................... 20
4. Detailed Description.................................................................................................................................. 24
4.1 Functional Overview .................................................................................................................... 24
4.2 Serial Digital Input ........................................................................................................................ 25
4.2.1 Integrated Adaptive Cable Equalizer.......................................................................... 25
4.3 Serial Digital Loop-Through Output ........................................................................................ 26
4.4 Serial Digital Reclocker ............................................................................................................... 26
4.4.1 PLL Loop Bandwidth ........................................................................................................ 26
4.5 External Crystal/Reference Clock ........................................................................................... 27
4.6 Lock Detect ...................................................................................................................................... 28
4.6.1 Asynchronous Lock .......................................................................................................... 29
4.6.2 Signal Interruption............................................................................................................ 30
4.7 SMPTE Functionality .................................................................................................................... 30
4.7.1 Descrambling and Word Alignment ........................................................................... 30
4.8 Parallel Data Outputs ................................................................................................................... 30
4.8.1 Parallel Data Bus Buffers................................................................................................. 30
4.8.2 Parallel Output in SMPTE Mode ................................................................................... 33
4.8.3 Parallel Output in DVB-ASI Mode ............................................................................... 33
4.8.4 Parallel Output in Data-Through Mode ..................................................................... 34
4.8.5 Parallel Output Clock (PCLK)......................................................................................... 34
4.9 Timing Signal Generator ............................................................................................................. 34
4.9.1 Manual Switch Line Lock Handling ............................................................................ 35
4.9.2 Automatic Switch Line Lock Handling....................................................................... 36
4.10 Programmable Multi-function Outputs ............................................................................... 38
4.11 H:V:F Timing Signal Generation ............................................................................................ 39
4.11.1 CEA-861 Timing Generation ....................................................................................... 40
4.12 Automatic Video Standards Detection ................................................................................ 46
4.12.1 2K Support......................................................................................................................... 49
4.13 Data Format Detection & Indication ..................................................................................... 50
4.14 EDH Detection .............................................................................................................................. 51
4.14.1 EDH Packet Detection ................................................................................................... 51
4.14.2 EDH Flag Detection ........................................................................................................ 51
GS1661A HD/SD SDI Receiver
Data Sheet
54387 - 2
September 2012
3 of 85


3Pages


GS1661A 電子部品, 半導体
List of Tables
Table 1-1: Pin Descriptions ............................................................................................................................ 7
Table 2-1: Absolute Maximum Ratings................................................................................................... 14
Table 2-2: Recommended Operating Conditions................................................................................ 14
Table 2-3: DC Electrical Characteristics ................................................................................................. 15
Table 2-4: AC Electrical Characteristics ................................................................................................. 16
Table 4-1: Serial Digital Output................................................................................................................. 26
Table 4-2: PLL Loop Bandwidth ................................................................................................................ 27
Table 4-3: Input Clock Requirements...................................................................................................... 28
Table 4-4: Lock Detect Conditions............................................................................................................ 29
Table 4-5: GS1661A Output Video Data Format Selections ............................................................ 32
Table 4-6: GS1661A PCLK Output Rates ................................................................................................ 34
Table 4-7: Switch Line Position for Digital Systems ........................................................................... 37
Table 4-8: Output Signals Available on Programmable Multi-Function Pins............................ 38
Table 4-9: Supported CEA-861 Formats................................................................................................. 41
Table 4-10: CEA861 Timing Formats....................................................................................................... 41
Table 4-11: Supported Video Standard Codes ..................................................................................... 47
Table 4-12: Data Format Register Codes ................................................................................................ 50
Table 4-13: Error Status Register and Error Mask Register .............................................................. 53
Table 4-14: IOPROC_DISABLE Register Bits ......................................................................................... 58
Table 4-15: GSPI Time Delay...................................................................................................................... 66
Table 4-16: GSPI Timing Parameters (50% levels; 3.3V or 1.8V operation) ................................ 67
Table 4-17: Configuration and Status Registers................................................................................... 68
Table 4-18: ANC Extraction FIFO Access Registers............................................................................ 76
Table 7-1: Packaging Data........................................................................................................................... 83
GS1661A HD/SD SDI Receiver
Data Sheet
54387 - 2
September 2012
6 of 85

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部品番号部品説明メーカ
GS1661A

HD/SD SDI Receiver

Semtech
Semtech


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