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PDF 74HC08 Data sheet ( Hoja de datos )
| Número de pieza | 74HC08 | |
| Descripción | Quad 2-Input AND Gate | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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74HC08
Quad 2−Input AND Gate
High−Performance Silicon−Gate CMOS
The 74HC08 is identical in pinout to the LS08. The device inputs are
compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 24 FETs or 6 Equivalent Gates
• These are Pb−Free Devices
1
A1
B1 2
4
A2
B2 5
9
A3
B3 10
12
A4
B4 13
LOGIC DIAGRAM
PIN 14 = VCC
PIN 7 = GND
3 Y1
6 Y2
Y = AB
8 Y3
11 Y4
Pinout: 14−Lead Packages (Top View)
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
14
1
http://onsemi.com
MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
HC08G
AWLYWW
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
HC
08
ALYW G
G
1
HC08 = Device Code
A = Assembly Location
WL or L = Wafer Lot
Y = Year
WW or W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
L
L
L
H
1234567
A1 B1 Y1 A2 B2 Y2 GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1
Publication Order Number:
74HC08/D
1 page  
74HC08
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
14
1
−T−
SEATING
PLANE
−A−
G
8
−B− P 7 PL
0.25 (0.010) M B M
7
C R X 45 _
F
D 14 PL
K
0.25 (0.010) M T B S A S
M
J
SOLDERING FOOTPRINT*
14X
0.58
7X
7.04
1
14X
1.52
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74HC08.PDF ] | |
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