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Datasheet IZE4406 PDF ( 特性, スペック, ピン接続図 )

部品番号 IZE4406
部品説明 Intelligent 104-Bit EEPROM Counter
メーカ Integral
ロゴ Integral ロゴ 
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IZE4406 Datasheet, IZE4406 PDF,ピン配置, 機能
IZE4406
Intelligent 104-Bit EEPROM Counter
for > 20000 Units with Security Logic
The chip contains an EEPROM/PROM of 88 bits, a mask ROM of 16 bits and a
sequencing control with security logic.
Memory (104 bits) is divided into the following functional areas
In the condition as supplied, the transport code and the error counter are activated. The
chip can only be read (except for the transport-code area) and only the error counter can
be written.
Following correct entry of the transport code, the entire memory can be read and areas II
and III can be written and EEPROM part of area III can be erased.
After the control flag has been written, everything is readable and only area III can be
programmed, but with the following changes:
- The transport code and the error counter are no longer activated.
- The area of the former transport code and the error counter can be erased byte by byte
with carry.
- The entire area III can be written bit by bit
NB: When the control flag is written, the counter stage below it (the error counter) can be
erased at the same time.
FEATURES
104 x 1 bit organization
Three memory areas with special characteristics (eg ROM, PROM, EEPROM)
Maximum of 20480 count units
Special security features
Minimum of 104 write/erase cycles
Data retention for minimum of ten years
Contact configuration and serial interface in accordance to ISO standard 7816-3
(synchronous transmission)
PIN DEFINITIONS AND FUNCTIONS
Card Contact Pad
Symbol
C7 01 I/O
02 P
C3 03 CLC
C2 04 RST
C1 05 Vcc
C6 N.C.
C5 06 GND
Function
Bidirectional data line (open drain)
Code entry on “Input” only for transport
Test input
Clock input
Control input (reset)
Supply voltage
Not connected
Ground
IZ4406 comes as an M1 wire-bonded module for embedding in plastic cards and as a die
for customer packaging
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IZE4406 pdf, ピン配列
IZE4406
DC CHARACTERISTICS
Parameter
Symbol
Limit Values
Unit Test
Condition
Min.
Typ.
Max.
SUPPLY
Supply voltage
Supply current
DATA INPUT
VCC 4.75
5
5.5
V
ICC 1.5 5 mA
-
-
H-Input voltage (I/O,CLC,P,RST)
VH
3.5
-
VCC
V
L-Input voltage (I/O,CLC,RST) VL 0
- 0.8 V
L-Input current (CLC)
IH -
- 100 µA
(VH=5 V, internal pull-down)
L-Input current (RST)
-IL -
- 100 µA
(VH=0 V, internal pull-up)
DATA OUTPUT
-
-
-
-
L-Output current
(VH=0.5 V, open drain)
H-Output current
(VH=5 V, open drain)
IL -
IH -
- 0.5 µA
- 10 µA
-
-
PULSE DURATION
RST (address reset)
RST (set R – flag)
CLC (count, H-level)
CLC (count, L-level)
CLC (write, H-level)
CLC (erase, H-level)
tR 50 -
tS 10 -
tH 10 -
tL 10 -
tHW 5 -
tHE 5 -
- µs
- µs
- µs
- µs
- ms
- ms
-
-
-
-
-
-
AC CHARACTERISTICS
Delay time
Delay time
Delay time
Delay time
Delay time
Delay time
Delay time
td1
td2
td9
td10
td3, td4,
td5
td6, td7
td8
5
3.5
5
5
3.5
5
10
-
-
-
-
-
-
-
- µs
- µs
- µs
- µs
- µs
- µs
- µs
-
-
-
-
-
-
-
CHIP PAD DIAGRAM
IZE4406
01
3


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