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Datasheet IZE4442 PDF ( 特性, スペック, ピン接続図 )

部品番号 IZE4442
部品説明 INTELLIGENT 256-BYTE EEPROM
メーカ Integral
ロゴ Integral ロゴ 
プレビュー
Total 21 pages
		
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IZE4442 Datasheet, IZE4442 PDF,ピン配置, 機能
IZE4442
INTELLIGENT 256-BYTE EEPROM WITH WRITE PROTECT FUNCTION
AND PROGRAMMABLE SECURITY CODE (PSC)
Features
256 x 8-bit EEPROM organization
Byte-wise addressing
Irreversible byte-wise write protection of lowest
32 addresses (Byte 0...31)
32 x 1-bit organization of protection memory
Two-wire link protocol
End of processing indicated at data output
Answer-to-Reset ace. to ISO standard 7816-3
Programming time 2.5 ms per byte for both erasing
and writing
Minimum of 104 write/erase cycles1)
Data retention for minimum of ten years1)
Contact configuration and serial interface in accordance
with ISO standard 7816 (synchronous transmission)
Additional Feature of IZE4442
Data can only be changed after entry of the correct 3-byte programmable security code (security memory)
Type
Ordering Code
Package
IZE4442 M2.2
on request
Wire-Bonded Module M2.2
IZE4442 C
on request
Chip
IZE4442 M2.2
on request
Wire-Bonded Module M2.2
IZE4442 C
on request
Chip
1) Values are temperature dependent, for further information please refer to your sales office.
Pin Configuration(top view)
(Card Contacts)Pin Definitions and Functions
Card Contact
Symbol
Function
C1
VCC
Supply voltage
C2 RST
Reset
C3 CLK Clock input
C4
N.C.
Not connected
C5 GND
Ground
C6
N.C.
Not connected
C7 I/O Bi-directional data line
(open drain)
C8
N.C.
Not connected
IZE4442 comes as a M2.2 wire-bonded module for embedding in plastic cards or as a die for customer
packaging.
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IZE4442 pdf, ピン配列
Functional Description Block Diagram
Memory Overview
IZE4442
Figure 1 Memory Overview
The IZE4442 consists of 256 x 8 bit EEPROM main memory and a 32-bit protection memory with PROM
functionality. The main memory is erased and written byte by byte. When erased, all 8 bits of a data byte are
set to logical one. When written, the information in the individual EEPROM cells is, according to the input
data, altered bit by bit to logical zeros, (logical AND between the old and the new data in the EEPROM).
Normally a data change consists of an erase and write procedure. It depends on the contents of the data
byte in the main memory and the new data byte whether the EEPROM is really erased and/or written. If
none of the 8 bits in the addressed byte requires a zero-to-one transition the erase access will be
suppressed. Vice versa the write access will be suppressed if no one-to-zero transition is necessary. The
write and the erase operation takes at least 2.5 ms each.
Each of the first 32 bytes can be irreversibly protected against data change by writing the corresponding bit
in the protection memory. Each data byte in this address range is assigned to one bit of the protection
memory and has the same address as the data byte in the main memory which it is assigned to. Once
written the protection bit cannot be erased (PRQM).
Additionally to the above functions the IZE4442 provides a security code logic which controls the write/erase
access to the memory. For this purpose the IZE4442 contains a 4-byte security memory with an Error
Counter EC (bit 0 to bit 2) and 3 bytes reference data. These 3 bytes as a whole are called Programmable
Security Code (PSC). After power on the whole memory, except for the reference data, can only be read.
Only after a successful comparison of verification data with the internal reference data the memory has the
identical access functionality of the IZE4442 until the power is switched off. After three successive
unsuccessful comparisons the Error Counter blocks any subsequent attempt, and hence any possibility to
write and erase.
2.2 Transmission Protocol
The transmission protocol is a two wire link protocol between the interface device IFD and the integrated
circuit IC. It is identical to the protocol type "S = A". All data changes on I/O are initiated by the falling edge
on CLK.
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IZE4442 電子部品, 半導体
IZE4442
Figure 4 Command Mode
The IZE4442 provides 7 commands which are listed in table 1 and 2
Table 1
Byte 1
Byte 2
Byte 3
Control
B7 B6 B5 B4 B3 B2 B1 B0
Address
A7 - A0
Data
D7 – D0
Operation
0 01 1 0 0 0 0
0 01 1 1 0 0 0
0 01 1 0 1 0 0
0 01 1 1 1 0 0
Table 2
00110001
address
address
no effect
address
no effect
no effect
input data
no effect
input data
READ MAIN
MEMORY
UPDATE MAIN
MEMORY
READ PROTECTION
MEMORY
WRITE
PROTECTION
MEMORY
no effect
READ SECURITY
MEMORY
00111001
address
input data UPDATE SECURITY
MEMORY
00110011
address
input data
COMPARE
VERIFICATION DATA
Mode
outgoing
data
processing
outgoing
data
processing
outgoing data
processing
processing
2.3.1 Read Main Memory
The command reads out the contents of the main memory (with LSB first) starting at the given byte address
(N = 0 ... 255) up to the end of the memory. After the command entry the IFD has to supply sufficient clock
pulses. The number of clocks is m = (256 - N) x 8 + 1. The read access to the main memory is always
possible.
Address
(decimal)
255
32
31
3
2
Main Memory
Data Byte 255 (D7...D0)
:
:
:
Data Byte 32 (D7...D0)
Data Byte 31 (D7...D0)
:
:
:
Data Byte 3 (D7...D0)
Data Byte 2 (D7...D0)
Protection Memory
-
-
Protection Bit 31 (D31)
Protection Bit 3 (D3)
Protection Bit 2 (D2)
Security Memory
-
-
-
Reference Data Byte 3 (D7...D0)
Reference Data Byte 2 (D7...D0)
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