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V826632K24SA の電気的特性と機能

V826632K24SAのメーカーはProMOS TECHNOLOGIESです、この部品の機能は「32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE」です。


製品の詳細 ( Datasheet PDF )

部品番号 V826632K24SA
部品説明 32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE
メーカ ProMOS TECHNOLOGIES
ロゴ ProMOS TECHNOLOGIES ロゴ 




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V826632K24SA Datasheet, V826632K24SA PDF,ピン配置, 機能
V826632K24SA
32M x 64 HIGH PERFORMANCE
UNBUFFERED DDR SDRAM MODULE
Features
184 Pin Unbuffered 33,554,432 x 64 bit
Organization DDR SDRAM Modules
Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
Single +2.5V (± 0.2V) Power Supply
Single +2.6V (± 0.1V) Power Supply for DDR400
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
8192 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Component Used D3 C0 B1 B0
tCK Clock Frequency
200
166
143 133
(max.)
(PC400) (PC333) (PC266A) (PC266B)
Module Speed
D0
tAC
Clock Cycle Time
6
CAS CLaloteckncFyre=q2u.e5ncy (max.)
6
7 7.5
200
(PC400A)
tAC ClockCCloycckleCTyicmleeTime C5AS Laten-cy = 2 -
tCCKAS
Latency = 3
Clock Cycle
Time
CAS
Latency
=
2.5
-7.5
5
Clock Cycle Time CAS Latency = 3
5
tRCD tRCD parameter
tRP tRP parameter
3
3
Description
The V826632K24SA memory module is
organized 33,554,432 x 64 bits in a 184 pin memory
module. The 32M x 64 memory module uses 8
ProMOS 32M x 8 DDR SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
D3
200
(PC400B)
7.5
6
5
3
3
C0
166
(PC333)
7.5
6
-
3
3
B1
143
(PC266A)
7.5
7
-
2
2
B0
133
(PC266B)
10
7.5
-
3
3
Units
MHz
ns
ns
ns
CLK
CLK
V826632K24SA Rev. 1.3 April 2006
1

1 Page





V826632K24SA pdf, ピン配列
ProMOS TECHNOLOGIES
V826632K24SA
Block Diagram
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS0
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D0
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D1
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
Clock Wiring
Clock Input SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
BA0-BA1
A0 - A12
RAS
CAS
CKE0
WE
V DD/ V DDQ
VREF
V SS
VDDID
BA0-BA1 : SDRAMs D0 - D7
A0 - A12 :SDRAMs D0 - D7
RAS : SDRAMs D0 - D7
CAS : SDRAMs D0 - D7
CKE : SDRAMs D0 - D7
WE : SDRAMs D0 - D7
0.1uF 0.1uF
0.1uF
D0 - D7
D0 - D7
D0 - D7
D0 - D7
Strap: see Note 4
SCL
Serial PD
A0 A1 A2
SDA
SA0
SA1 SA2
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ,DQS, DM/DQS resistors : 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ) :
STRAP OUT (OPEN): VDD=VDDQ
STRAP IN (VSS): VDD VDDQ
V826632K24SA Rev.1.3 April 2006
3


3Pages


V826632K24SA 電子部品, 半導体
ProMOS TECHNOLOGIES
V826632K24SA
Serial Presence Detect Information (cont.)
Byte
#
Function described
Function Supported
D0 D3 C0 B1 B0
Hex value
D0 D3 C0 B1 B0
25 DDR SDRAM cycle time at third highest CL 7.5ns 7.5ns - - - 75h 75h 00h 00h 00h
26 DDR SDRAM Access time from clock at third high-±0.75ns ±0.75ns - - - 75h 75h 00h 00h 00h
est CL
27 Minimum row precharge time (=tRP)
15ns 15ns 18ns 15ns 20ns 3Ch 3Ch 48h 3Ch 50h
28 Minimum row activate to row active delay (=tRRD) 10ns 10ns 12ns 15ns 15ns 28h 28h 30h 3Ch 3Ch
29 Minimum RAS to CAS delay (=tRCD)
15ns 15ns 18ns 15ns 20ns 3Ch 3Ch 48h 3Ch 50h
30 Minimum active to precharge time (=tRAS)
40ns 40ns 42ns 45ns 45ns 28h 28h 2Ah 2Dh 2Dh
31 Module ROW density
256MB
40h
32 Command and address signal input setup time 0.6ns 0.6ns 0.75ns 0.9ns 0.9ns 60h 60h 75h 90h 90h
33 Command and address signal input hold time 0.6ns 0.6ns 0.75ns 0.9ns 0.9ns 60h 60h 75h 90h 90h
34 Data signal input setup time
0.4ns 0.4ns 0.45ns 0.5ns 0.5ns 40h 40h 45h 50h 50h
35 Data signal input hold time
0.4ns 0.4ns 0.45ns 0.5ns 0.5ns 40h 40h 45h 50h 50h
36-40 Superset information (may be used in future)
00h
41 SDRAM device minimum active to active/auto-re- 60ns 60ns 60ns 65ns 65ns 3Ch 3Ch 3Ch 41h 41h
fresh time (=tRC)
42 SDRAM device minimum active to autorefresh to 70ns 70ns 72ns 75ns 75ns 46h 46h 48h 4Bh 4Bh
active/auto-refresh time (=tRFC)
43 SDRAM device maximum device cycle time (=tCK 12ns 12ns 12ns 12ns 12ns 30h 30h 30h 30h 30h
MAX)
44 SDRAM device maximum skew between DQS
and DQ signals (=tDQSQ)
0.4ns 0.4ns 0.45ns 0.5ns 0.5ns 28h 28h 2Dh 32h 32h
45 SDRAM device maximum read datahold skew
factor (=tQHS)
0.55ns 0.55ns 0.60ns 0.75ns 0.75ns 55h 55h 60h 75h 75h
46-61 Superset information (may be used in future)
-
00h
62 SPD data revision code
Initial release
11h 11h 00h 00h 00h
63 Checksum for Bytes 0 ~ 62
- A3h BEh 4Bh CAh 22h
64 Manufacturer JEDEC ID code
ProMOS
40h
65 -71 ....... Manufacturer JEDEC ID code
00h
72 Manufacturing location
02=Taiwan 05=China 0A=S-CH
73-90 Module part number (ASCII)
V826632K24SA
91 Manufacturer revison code (For PCB)
0
00
92 Manufacturer revison code (For component)
0
00
93 Manufacturing date (Year)
--
94 Manufacturing date (Week)
--
95~98 Assembly serial #
--
V826632K24SA Rev. 1.3 April 2006
6

6 Page



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部品番号部品説明メーカ
V826632K24S

2.5 VOLT 32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE

Mosel Vitelic  Corp
Mosel Vitelic Corp
V826632K24SA

32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE

ProMOS TECHNOLOGIES
ProMOS TECHNOLOGIES


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