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PDF STM8L051F3 Data sheet ( Hoja de datos )
| Número de pieza | STM8L051F3 | |
| Descripción | 8-bit ultralow power MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STM8L051F3
Value line, 8-bit ultralow power MCU, 8-KB Flash,
256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC
Data brief preliminary data
Features
■ Operating conditions
– Operating power supply: 1.8 V to 3.6 V
Temperature range: 40 °C to 85 °C
■ Low power features
– 5 low power modes: Wait, Low power run,
Low power wait, Active-halt with RTC, Halt
– Ultralow leakage per I/0: 50 nA
– Fast wakeup from Halt: 5 µs
■ Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq: 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
■ Reset and supply management
– Low power, ultrasafe BOR reset with 5
selectable thresholds
– Ultra low power POR/PDR
– Programmable voltage detector (PVD)
■ Clock management
– 32 kHz and 1 to 16 MHz crystal oscillators
– Internal 16 MHz factory-trimmed RC
– Internal 38 kHz low consumption RC
– Clock security system
■ Low power RTC
– BCD calendar with alarm interrupt
– Digital calibration with +/- 0.5 ppm accuracy
– LSE security system
– Auto-wakeup from Halt w/ periodic interrupt
■ Memories
– 8 Kbytes of Flash program memory and
256 bytes of data EEPROM with ECC
– Flexible write and read protection modes
– 1 Kbyte of RAM
TSSOP20
■ DMA
– 4 channels supporting ADC, SPI, I2C,
USART, timers
– 1 channel for memory-to-memory
■ 12-bit ADC up to 1 Msps/28 channels
– Internal reference voltage
■ Timers
– Two 16-bit timers with 2 channels (used as
IC, OC, PWM), quadrature encoder
– One 8-bit timer with 7-bit prescaler
– 2 watchdogs: 1 Window, 1 Independent
– Beeper timer with 1, 2 or 4 kHz frequencies
■ Communication interfaces
– Synchronous serial interface (SPI)
– Fast I2C 400 kHz SMBus and PMBus
– USART
■ Up to 18 I/Os, all mappable on interrupt vectors
■ Development support
– Fast on-chip programming and non-
intrusive debugging with SWIM
– Bootloader using USART
Table 1. Device summary
Reference
Part number
STM8L051xx
STM8L051F3
April 2012
Doc ID 022985 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice. For further information contact your local STMicroelectronics sales office.
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www.st.com
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STM8L051F3
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Low density value line STM8L05xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . 10
Low density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM8L051Fx 20-pin TSSOP20 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSSOP20 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LQFP32 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Low density value line STM8L05xxx ordering information scheme . . . . . . . . . . . . . . . . . . 44
Doc ID 022985 Rev 1
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5 Page 
STM8L051F3
Functional overview
3.1 Low power modes
The low density value line STM8L05xxx devices support five low power modes to achieve
the best compromise between low power consumption, short startup time and available
wakeup sources:
● Wait mode: The CPU clock is stopped, but selected peripherals keep running. An
internal or external interrupt or a Reset can be used to exit the microcontroller from
Wait mode (WFE or WFI mode).
● Low power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra low power mode.
The microcontroller enters Low power run mode by software and can exit from this
mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
● Low power wait mode: This mode is entered when executing a Wait for event in Low
power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the
system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
● Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset.
● Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.
Doc ID 022985 Rev 1
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