PDF STM32F756IE Data sheet ( Hoja de datos )

Número de pieza	STM32F756IE
Descripción	32-bit MCU + FPU
Fabricantes	STMicroelectronics
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STM32F756xx ARM®-based Cortex®-M7 32b MCU+FPU, 428DMIPS, up to 1MB Flash/320+16+ 4KB RAM, crypto, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD Data brief Features • Core: ARM® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator™) and L1 cache: 4KB data cache and 4KB instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 200 MHz, MPU, 428 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. • Memories – Up to 1MB of Flash memory – SRAM: 320KB (including 64KB of data TCM RAM for critical real time data) + 16KB of instruction TCM RAM (for critical real time routines) + 4KB of backup SRAM (available in the lowest power modes) – Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories • Dual mode Quad SPI • LCD parallel interface, 8080/6800 modes • LCD-TFT controller up to XGA resolution with dedicated Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D) • Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – Dedicated USB power – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VreBgAisTtseurspp+ly4KfoBr RTC, 32×32 bit backup SRAM backup • 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 18 timers: up to thirteen 16-bit (1x low power 16-bit timer available in stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 200 MHz. 2x watchdogs, SysTick timer &"'! LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) UFBGA176 (10 x 10 mm) WLCSP143 LQFP176 (24 × 24 mm) LQFP208 (28 x 28 mm) TFBGA216 (13 x 13 mm) • Debug mode – SWD & JTAG interfaces – Cortex®-M7 Trace Macrocell™ • Up to 168 I/O ports with interrupt capability – Up to 164 fast I/Os up to 100 MHz – Up to 166 5 V-tolerant I/Os • Up to 25 communication interfaces – Up to 4× I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/4 UARTs (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Umpuxtoed6sSimPpIsle(xupI2tSo 50 for Mbits/s), 3 with audio class accuracy via internal audio PLL or external clock – 2 x SAI (serial audio interface) – 2 × CAN (2.0B Active) and SDMMC interface – SPDIF-IN interface – HDMI-CEC • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • Cryptographic acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1, SHA-2), and HMAC • True random number generator • CRC calculation unit • RTC: subsecond accuracy, hardware calendar • 96-bit unique ID Table 1. Device summary Reference Part number STM32F756xx STM32F756VG, STM32F756ZG, STM32F756IG, STM32F756BG, STM32F756NG, STM32F756IE, STM32F756VE, STM32F756ZE, STM32F756BE, STM32F756NE November 2014 DocID026379 Rev 2 For further information contact your local STMicroelectronics sales office. 1/108 www.st.com 1 page STM32F756xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F756xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 21 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 24 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F756xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STM32F756xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 STM32F756xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 87 WLCSP143, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . 90 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 106 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 DocID026379 Rev 2 5/108 5 5 Page STM32F756xx Description Figure 2. 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The timers connected to APB2 are clocked from TIMxCLK up to 200 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 100 MHz or 200 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. DocID026379 Rev 2 11/108 38 11 Page

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Hoja de datos destacado

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