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74HC05-Q100 の電気的特性と機能

74HC05-Q100のメーカーはNXP Semiconductorsです、この部品の機能は「Hex inverter」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HC05-Q100
部品説明 Hex inverter
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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74HC05-Q100 Datasheet, 74HC05-Q100 PDF,ピン配置, 機能
74HC05-Q100
Hex inverter with open-drain outputs
Rev. 1 — 9 July 2012
Product data sheet
1. General description
The 74HC05-Q100 is a high-speed Si-gate CMOS device that complies with JEDEC
standard no. 7A.
The 74HC05-Q100 contains six inverters. The outputs of the 74HC05-Q100 are
open-drain and can be connected to other open-drain outputs to implement active-LOW
wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up
resistors to perform correctly.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide operating voltage 2.0 V to 6.0 V
Input levels:
For 74HC05-Q100: CMOS level
Latch-up performance exceeds 100 mA per JESD 78 Class II level A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Multiple package options

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74HC05-Q100 pdf, ピン配列
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
5. Pinning information
5.1 Pinning
74HC05-Q100
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
14 VCC
13 6A
12 6Y
11 5A
10 5Y
9 4A
8 4Y
aaa-003361
Fig 3. Pin configuration SOT108-1 (SO14)
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
74HC05-Q100
14 VCC
13 6A
12 6Y
11 5A
10 5Y
9 4A
8 4Y
aaa-003362
Fig 4. Pin configuration SOT402-1 (TSSOP14)
74HC05-Q100
terminal 1
index area
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND(1)
13 6A
12 6Y
11 5A
10 5Y
9 4A
aaa-003363
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration SOT762-1 (DHVQFN14)
5.2 Pin description
Table 2.
Symbol
1A to 6A
1Y to 6Y
GND
VCC
Pin description
Pin
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
7
14
Description
data input
data output
ground (0 V)
supply voltage
74HC05_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 July 2012
© NXP B.V. 2012. All rights reserved.
3 of 15


3Pages


74HC05-Q100 電子部品, 半導体
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter
Conditions
Min
tPLZ LOW to OFF-state nA to nY; see Figure 6
propagation delay VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tPZL OFF-state to LOW nA to nY; see Figure 6
propagation delay VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tTHL HIGH to LOW see Figure 6
output transition
time
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
CPD
power dissipation per inverter; VI = GND to VCC;
[1]
capacitance
VCC = 5.0 V
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (0.5 CL VO2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
VO = output voltage in V (output HIGH);
VCC = supply voltage in V;
N = number of inputs switching;
RL = load resistance in M;
CL = load capacitance in pF;
-
-
-
-
-
-
-
-
-
-
25 C
Typ
20
11
10
22
9
8
18
6
5
4
40 C to +125 C Unit
Max Max
Max
(85 C) (125 C)
90 115 135 ns
18 23
27 ns
15 20
23 ns
90 115 135 ns
18 23
27 ns
15 20
23 ns
75 95 110 ns
15 19
22 ns
13 16
19 ns
--
- pF
74HC05_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 July 2012
© NXP B.V. 2012. All rights reserved.
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部品番号部品説明メーカ
74HC05-Q100

Hex inverter

NXP Semiconductors
NXP Semiconductors


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