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GAL16V8A-10LJI の電気的特性と機能

GAL16V8A-10LJIのメーカーはLattice Semiconductorです、この部品の機能は「HIGH PERFORMANCE E2CMOS PLD」です。


製品の詳細 ( Datasheet PDF )

部品番号 GAL16V8A-10LJI
部品説明 HIGH PERFORMANCE E2CMOS PLD
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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GAL16V8A-10LJI Datasheet, GAL16V8A-10LJI PDF,ピン配置, 機能
GAL16V8
High Performance E2CMOS PLD
Generic Array Logic™
Features
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
3.5 ns Maximum Propagation Delay
Fmax = 250 MHz
3.0 ns Maximum from Clock Input to Data Output
UltraMOS® Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
75mA Typ Icc on Low Power Device
45mA Typ Icc on Quarter Power Device
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
Maximum Flexibility for Complex Logic Designs
Programmable Output Polarity
Also Emulates 20-pin PAL® Devices with Full
Function/Fuse Map/Parametric Compatibility
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
100% Functional Testability
APPLICATIONS INCLUDE:
DMA Control
State Machine Control
High Speed Graphics Processing
Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL16V8, at 3.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL16V8 are the PAL architectures listed
in the table of the macrocell description section. GAL16V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
I/CLK
CLK
I
I
I
I
I
I
I
I
Pin Configuration
I
I4
PLCC
I I/CLK Vcc I/O/Q
2 20
18
I/O/Q
I GAL16V8 I/O/Q
I6
16 I/O/Q
Top View
I I/O/Q
I8
9
14 I/O/Q
11 13
I GND I/OE I/O/Q I/O/Q
I/CLK
I
I
I
I
I
I
I
I
GND
SOIC
1 20
GAL
5 16V8
Top 15
View
10 11
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
OE
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
DIP
I/CLK
I
I
I
I
I
I
I
I
GND
1 20 Vcc
I/O/Q
GAL
16V8
5
I/O/Q
I/O/Q
I/O/Q
15 I/O/Q
I/O/Q
I/O/Q
I/O/Q
10 11 I/OE
Copyright © 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 2001
16v8_08
1

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GAL16V8A-10LJI pdf, ピン配列
Specifications GAL16V8
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
are illustrated in the following pages. Two global bits, SYN and
AC0, control the mode configuration for all macrocells. The XOR
bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls
the input/output configuration. These two global and 16 individ-
ual architecture bits define all possible configurations in a GAL16V8
. The information given on these architecture bits is only to give
a better understanding of the device. Compiler software will trans-
parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.
PAL Architectures
Emulated by GAL16V8
16R8
16R6
16R4
16RP8
16RP6
16RP4
16L8
16H8
16P8
10L8
12L6
14L4
16L2
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
GAL16V8
Global OLMC Mode
Registered
Registered
Registered
Registered
Registered
Registered
Complex
Complex
Complex
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Compiler Support for OLMC
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft-
ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured
Registered
ABEL
CUPL
LOG/iC
OrCAD-PLD
PLDesigner
TANGO-PLD
P16V8R
G16V8MS
GAL16V8_R
"Registered"1
P16V8R2
G16V8R
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
Complex
P16V8C
G16V8MA
GAL16V8_C7
"Complex"1
P16V8C2
G16V8C
Simple
P16V8AS
G16V8AS
GAL16V8_C8
"Simple"1
P16V8C2
G16V8AS3
Auto Mode Select
P16V8
G16V8
GAL16V8
GAL16V8A
P16V8A
G16V8
3


3Pages


GAL16V8A-10LJI 電子部品, 半導体
Specifications GAL16V8
Complex Mode
In the Complex mode, macrocells are configured as output only or bility. Designs requiring eight I/O's can be implemented in the
I/O functions.
Registered mode.
Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product
common 16L8 and 16P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and
each macrocell.
11 are always available as data inputs into the AND array.
Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses
outputs can be implemented as subsets of the I/O function. The are shown on the logic diagram on the following page.
two outer most macrocells (pins 12 & 19) do not have input capa-
XOR
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 13 through Pin 18 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 12 and Pin 19 are configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
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共有リンク

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部品番号部品説明メーカ
GAL16V8A-10LJ

HIGH PERFORMANCE E2CMOS PLD

Lattice Semiconductor
Lattice Semiconductor
GAL16V8A-10LJI

HIGH PERFORMANCE E2CMOS PLD

Lattice Semiconductor
Lattice Semiconductor


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