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PDF FDC37M605 Data sheet ( Hoja de datos )

Número de pieza FDC37M605
Descripción ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
Fabricantes SMSC Corporation 
Logotipo SMSC Corporation Logotipo



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No Preview Available ! FDC37M605 Hoja de datos, Descripción, Manual

FDC37M60x
Enhanced Super I/O Controller with Infrared Support
FEATURES
5 Volt Operation
PC98/99 and ACPI 1.0 Compliant
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
- Shadowed Write-Only Registers for
ACPI Compliance
2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk
Controller
- Software and Register Compatible
with SMSC's Proprietary 82077AA
Compatible Core
- Supports Two Floppy Drives Directly
- Configurable Open Drain/Push-Pull
Output Drivers
- Supports Vertical Recording Format
- 16-Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- 480 Address, Up to 15 IRQ and Three
DMA Options
Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300
Kbps, 250 Kbps Data Rates
- Programmable Precompensation
Modes
Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated
for Keyboard/Mouse Interface
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Counter Timer
- Port 92 Support
- 8042 P12 and P16 Outputs
Serial Ports
- Two Full Function Serial Ports
- High Speed NS16C550 Compatible
UARTs with Send/Receive 16-Byte
FIFOs
- Supports 230k and 460k Baud
Programmable Baud Rate Generator
Modem Control Circuitry
- 480 Address and 15 IRQ Options
Infrared Port
- Multiprotocol Infrared Interface
- IrDA 1.0 Compliant
- TEMIC/HP Module Support
- SHARP ASK IR
- 480 Address, Up to 15 IRQ Options
Multi-Mode™ Parallel Port with
ChiProtect™
- Standard Mode IBM PC/XT®, PC/AT®,
and PS/2™ Compatible Bidirectional
Parallel Port

1 page




FDC37M605 pdf
PIN CONFIGURATION
DRVDEN0
DRVDEN1
nMTRO
nDS1
nDS0
nMTR1
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
nDSKCHG
VCC
CLOCKI
nCS/SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FDC37M60x
100 PIN QFP
80 PE
79 SLCT
78 nERROR
77 nACK
76 VSS
75 PD0
74 PD1
73 PD2
72 PD3
71 PD4
70 PD5
69 PD6
68 PD7
67 nINIT
66 nSLCTIN
65 VCC
64 KBDRST
63 A20M
62 IRTX
61 IRRX
60 VSS
59 KDAT
58 KCLK
57 MDAT
56 MCLK
55 IOCHRDY
54 TC
53 VCC
52 DRQ3/P12
51 nDACK3/P16
5

5 Page





FDC37M605 arduino
FUNCTIONAL DESCRIPTION
SUPER I/O REGISTERS
HOST PROCESSOR INTERFACE
The address map, shown below in Table 1,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, serial and parallel
ports can be moved via the configuration
registers. Some addresses are used to access
more than one register.
The host processor communicates with the
FDC37M60x through a series of read/write
registers. The port addresses for these registers
are shown in Table 1. Register access is
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide. All host
interface output buffers are capable of sinking a
minimum of 24 mA.
Table 1 - Super I/O Block Addresses
LOGICAL
ADDRESS
BLOCK NAME
DEVICE
Base+(0-5) and +(7)
Floppy Disk
0
Base+(0-7)
Serial Port Com 1
4
Base1+(0-7)
Serial Port Com 2
5
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
3
60, 64
KYBD
7
NOTES
IR Support
Note 1: Refer to the configuration register descriptions for setting the base address
11

11 Page







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