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G1-266P-85-1.8 の電気的特性と機能

G1-266P-85-1.8のメーカーはNational Semiconductorです、この部品の機能は「Processor Series Low Power Integrated x86 Solution」です。


製品の詳細 ( Datasheet PDF )

部品番号 G1-266P-85-1.8
部品説明 Processor Series Low Power Integrated x86 Solution
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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G1-266P-85-1.8 Datasheet, G1-266P-85-1.8 PDF,ピン配置, 機能
April 2000
Geode™ GX1 Processor Series
Low Power Integrated x86 Solution
General Description
The National Semiconductor® Geode™ GX1 processor
series is a line of integrated processors specifically
designed to power information appliances for entertain-
ment, education, and business. Serving the needs of con-
www.DataSheet4Ussuo.cmluomteiorsn
and business professionals alike, it’s the perfect
for IA (information appliance) applications such as
thin clients, interactive set-top boxes, and personal internet
access devices.
The Geode GX1 processor series is divided into three main
categories as defined by the core operating voltage. Avail-
able with core voltages of 2.0V, 1.8V, and 1.6V, it offers
extremely low typical power consumption (1.2W, 1.0W, and
0.8W, respectively) leading to longer battery life and
enabling small form-factor, fanless designs. Typical power
consumption is defined as an average, measured running
Microsoft Windows at 80% Active Idle (Suspend-on-Halt)
with a display resolution of 800x600x8 bpp at 75 Hz.
Geode™ GX1 Processor Internal Block Diagram
SYSCLK
Clock Module
SYSCLK
multiplied
by “A”
Core
Clocks
X-Bus
Clocks
16 KB
Unified L1
Cache
(128)
C-Bus (64)
x86 Compatible Core
Integer
TLB Unit
Instruction
Fetch
MMU
Load/Store
INT/NMI
Interrupt
Control
FP_Error
Floating Point
Unit
INTR
IRQ13
SMI#
SUSP#
SUSPA#
Power
Management
Control
Core Suspend
Core Acknowledge
X-Bus Suspend
X-Bus Acknowledge
X-Bus (32)
Arbiter
Write
Buffers
X-Bus
Controller
Read
Buffers
Arbiter
PCI Host
Controller
2D Accelerator
VGA
BLT Engine
ROP Unit
X-Bus CLK
divide by “B”
Display Controller
Compression Buffer
Palette RAM
Timing Generator
3
REQ/GNT
Pairs
PCI
Bus
4
SDRAM
Clocks
64-bit
SDRAM
RGB
YUV
Geode™ Graphics
Companion Interface
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode, WebPAD, and VSA, are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
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G1-266P-85-1.8 pdf, ピン配列
Flexible Power Management
 Supports a wide variety of standards:
— APM (Advanced Power Management) for Legacy
power management
— ACPI (Advanced Configuration and Power Interface)
for Windows power management
– Direct support for all standard processor (C0-C4)
states
— OnNOW design initiative compliant
 Supports a wide variety of hardware and software
controlled modes:
— Active Idle (core-only stopped, display active)
— Standby (core and all integrated functions halted)
— Sleep (core and integrated functions halted and all
external clocks stopped)
www.DataSheet4U.comSuspend Modulation (automatic throttling of CPU
core via Geode I/O or graphics companion chip)
– Programmable duty cycle for optimal performance/
thermal balancing
— Several dedicated and programmable wake-up
events (via Geode I/O or graphics companion chip)
PCI Host Controller
 Several arbitration schemes supported
 Directly supports up to three PCI bus masters, more with
external logic
 Synchronous to CPU core
 Allows external PCI master accesses to main memory
concurrent with CPU accesses to L1 cache
Virtual Systems Architecture Technology
 Innovative architecture allowing OS independent (soft-
ware) virtualization of hardware functions
 Provides XpressGRAPHICS subsystem:
— High performance legacy VGA core compatibility
Note: The GUI acceleration is pure hardware.
 Provides 16-bit XpressAUDIO subsystem:
— 16-bit stereo FM synthesis
— OPL3 emulation
— Supports MPU-401 MIDI interface
— Hardware assist provided via Geode I/O companion
chip
 Additional hardware functions can be supported as
needed
2D Graphics Accelerator
 Accelerates BitBLTs, line draw, text:
— Bresenham vector engine
 Supports all 256 Raster Operations (ROPs)
 Supports transparent BLTs and page flipping for
Microsoft’s DirectDraw
 Runs at core clock frequency
 Full VGA and VESA mode support
 Special "driver level” instructions utilize internal
scratchpad for enhanced performance
Display Controller
 Display Compression Technology (DCT) architecture
greatly reduces memory bandwidth consumption of
display refresh
 Supports a separate video buffer and data path to
enable video acceleration in Geode I/O and graphics
companion chips
 Internal palette RAM for gamma correction
 Direct interface to Geode I/O and graphics companion
chips for CRT and TFT flat panel support eliminates the
need for an external RAMDAC
 Hardware cursor
 Supports up to 1280x1024x8 bpp and 1024x768x16 bpp
XpressRAM
 SDRAM interface tightly coupled to CPU core and
graphics subsystem for maximum efficiency
 64-Bit wide memory bus
 Support for:
— Two 168-pin unbuffered DIMMs
— Up to 16 simultaneously open banks
— 16-byte reads (burst length of two)
— Up to 512 MB total memory supported
Diverse Operating System Support
 Microsoft’s Windows 2000, Windows 95, Windows 98,
and Windows NT in non PC applications; along with
Windows CE and Windows NTE
 WindRiver System’s VxWorks
 QNX Software Systems’ QNX
 Linux
Revision 1.0
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G1-266P-85-1.8 電子部品, 半導体
Table of Contents (Continued)
4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.1
4.2
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4.3
4.4
INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.1 Graphics Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.3 Graphics Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.4 Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.1 Initialization of Scratchpad RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.2 Scratchpad RAM Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.3 BLT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.5 Display Driver Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.6 CPU_READ/CPU_WRITE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.1 FPU Error Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.2 A20M Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.3 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.4 640 KB to 1 MB Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.5 Internal Bus Interface Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.1 Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3.2 Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3.3 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.3.1 SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.3.4 Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.5 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.1 High Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.2 Auto Low Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.3 Physical Address to DRAM Address Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.6 Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3.7 SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.1 BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.2 Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3 Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3.1 Monochrome Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.2 Dither Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.3 Color Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.4 Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.5 Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.6 Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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共有リンク

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部品番号部品説明メーカ
G1-266P-85-1.8

Processor Series Low Power Integrated x86 Solution

National Semiconductor
National Semiconductor


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