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GD25Q10 の電気的特性と機能

GD25Q10のメーカーはGigaDeviceです、この部品の機能は「Dual and Quad SPI Flash」です。


製品の詳細 ( Datasheet PDF )

部品番号 GD25Q10
部品説明 Dual and Quad SPI Flash
メーカ GigaDevice
ロゴ GigaDevice ロゴ 




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Total 30 pages

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GD25Q10 Datasheet, GD25Q10 PDF,ピン配置, 機能
Uniform Sector
Dual and Quad SPI Flash
GD25Q40/20/10/512
FEATURES
4M/2M/1M/512K-bit Serial Flash
-512/256/128/64K-byte
-256 bytes per programmable page
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI:SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI:SCLK, CS#, IO0, IO1, IO2, IO3
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
Program/Erase Speed
-Page Program time:0.7ms typical
-Sector Erase time:150ms typical
-Block Erase time:0.3\0.5s typical
-Chip Erase time:3\2\1\0.5s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64K-byte
Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
Software/Hardware Write Protection
Advanced security Features(1)
-Write protect all/portion of memory via software
-16-Bit Customer ID
-Enable/Disable protection with WP# Pin
-Security Architecture
-Top or Bottom, Sector or Block selection
Single Power Supply Voltage
Minimum 100,000 Program/Erase Cycles
-Full voltage range:2.7~3.6V
Note: 1.Please contact Gigadevice for details.
GENERAL DESCRIPTION
The GD25Q40/20/10/512 (4M-bit) SPI flash supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual/Quad output as well as Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO),
I/O2 (WP#), and I/O3 (HOLD#). SPI clock frequencies of up to 120MHz are supported allowing equivalent clock rates of
240MHz for Dual Output & Dual I/O read command, and 480MHz for Quad output & Quad I/O read command.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1

1 Page





GD25Q10 pdf, ピン配列
Uniform Sector
Dual and Quad SPI Flash
MEMORY ORGANIZATION
GD25Q40
Each device has
Each block has
512K
64/32K
2K 256/128
128 16/8
8/16 -
Each sector has
4K
16
-
-
GD25Q20
Each device has
256K
1K
64
4/8
Each block has
64/32K
256/128
16/8
-
Each sector has
4K
16
-
-
GD25Q10
Each device has
128K
512
32
2/4
Each block has
64/32K
256/128
16/8
-
Each sector has
4K
16
-
-
GD25Q512
Each device has
64K
256
16
2
Each block has
32K
128
8
-
Each sector has
4K
16
-
-
GD25Q40/20/10/512
Each page has
256
-
-
-
bytes
pages
sectors
blocks
Each page has
256
-
-
-
bytes
pages
sectors
blocks
Each page has
256
-
-
-
bytes
pages
sectors
blocks
Each page has
256
-
-
-
bytes
pages
sectors
blocks
3


3Pages


GD25Q10 電子部品, 半導体
Uniform Sector
Dual and Quad SPI Flash
GD25Q40/20/10/512
DEVICE OPERATION
SPI Mode
Standard SPI
The GD25Q40/20/10/512 feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched
on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q40/20/10/512 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the
rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and
IO1.
Quad SPI
The GD25Q40/20/10/512 supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast
Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from
the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the
non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
6

6 Page



ページ 合計 : 30 ページ
 
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共有リンク

Link :


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GD25Q10

Dual and Quad SPI Flash

GigaDevice
GigaDevice
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GD25Q128B

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GD25Q128B

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