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PDF VS1063a Data sheet ( Hoja de datos )
| Número de pieza | VS1063a | |
| Descripción | HARDWARE GUIDE | |
| Fabricantes | VLSI | |
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VS1063a HW Guide
VS1063a HARDWARE GUIDE
MP3/OGG/AAC/WMA/FLAC/
G.711/G.722 AUDIO CODEC CIRCUIT
Key Features
Description
• Encoders:
VS1063a is an easy-to-use, versatile encoder,
MP3; Ogg Vorbis; PCM; IMA ADPCM; decoder and codec for a multitude of audio
G.711 (µ-law, A-law); G.722 ADPCM
formats.
• Decoders:
MP3 (MPEG 1 & 2 audio layer III (CBR VS1063a contains a high-performance, pro-
+VBR +ABR));
prietary low-power DSP core VS_DSP4, ROM
MP2 (layer II) (optional);
memories, 16 KiB instruction RAM and upto
MPEG4 / 2 AAC-LC(+PNS),
80 KiB data RAM for user applications run-
HE-AAC v2 (Level 3) (SBR + PS);
ning simultaneously with any built-in decoder,
Ogg Vorbis; FLAC;
serial control and input data interfaces, upto
WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps); 12 general purpose I/O pins, a UART, as well
WAV (PCM, IMA ADPCM, G.711 µ-law/A- as a high-quality variable-sample-rate stereo
law, G.722 ADPCM)
DAC and a stereo ADC, followed by an ear-
• Full Duplex Codecs:
phone amplifier and a common voltage buffer.
PCM; G.711 (µ-law, A-law); G.722 ADPCM;
IMA ADPCM
VS1063a can act both as an “MP3 decoder
• Streaming support
IC” or “MP3 encoder IC” slave in a system
• Upto 96 KiB RAM for user code and data with a microcontroller, or as a stand-alone cir-
• Unique ID for user code protection
cuit that boots from external SPI memory.
• Quiet power-on and power-off
• I2S output interface for external DAC
Applications
• Serial control and data interfaces
• Can be used either as a slave co-processor
or as a standalone processor
• UART for debugging purposes
• New functions may be added with soft-
• MP3-recording audio player
• Streaming server and client
• Wireless audio transfer
• Standalone player and recorder
ware and upto 12 GPIO pins
• Internet phones
Version: 1.15, 2014-12-19
1
1 page  
VS1063a HW Guide
LIST OF FIGURES
List of Figures
1 VS1063a DAC data paths with some data registers . . . . . . . . . . . . . . . . . 9
2 VS1063a ADC data paths with some data registers . . . . . . . . . . . . . . . . . 10
3 RS232 serial interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 I2S interface, 192 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Version: 1.15, 2014-12-19
5
5 Page 
VS1063a HW Guide
7 HARDWARE REGISTERS
7 Hardware Registers
VS1063a registers are memory mapped to X data memory, starting from address 0xC000.
7.1 Serial Control Interface (SCI)
SCI registers are mapped to X memory addresses between 0xC000..0xC00F. In addition to
these registers, there is one in address 0xC010, called SCI_CHANGE.
Only 3 of these 17 registers contain direct hardware control. Those registers and their hardware
registers bits are described in this section. For documentation of the software register bits, see
the VS1063a Datasheet.
7.1.1 SCI Hardware Registers
Reg
0xC000
0xC001
0xC010
Type
rw
rw
r
Reset
0x40002
0x000C2
0x00
SCI registers
Abbrev[bits]
Description
SCI_MODE
Mode control
SCI_STATUS
Status of VS1063a
SCI_CHANGE[5:0] Last SCI access address
1 Firmware changes the value of this register immediately to 0x4800.
2 Firmware changes the value of this register immediately to 0x48 (analog enabled), and after
a short while to 0x40 (analog drivers enabled).
7.1.2 Mode SCI_MODE (RW)
Name
SCI_MODE bits
Bit Function
Value Description
SM_DACT
8 DCLK active edge
0 rising
1 falling
SM_SDIORD
9 SDI bit order
0 MSb first
1 MSb last
SM_SDISHARE 10 Share SPI chip select
0 no
1 yes
SM_SDINEW
11 VS1002 native SPI modes 0 no
1 yes
SM_LINE1
14 MIC / LINE1 selector
SM_CLK_RANGE 15 Input clock range
0 MICP
1 LINE1
0 12..13 MHz
1 24..26 MHz
Version: 1.15, 2014-12-19
11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet VS1063a.PDF ] | |
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