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VS23S010CのメーカーはVLSIです、この部品の機能は「1 Megabit SPI SRAM」です。 |
部品番号 | VS23S010C |
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部品説明 | 1 Megabit SPI SRAM | ||
メーカ | VLSI | ||
ロゴ | |||
このページの下部にプレビューとVS23S010Cダウンロード(pdfファイル)リンクがあります。 Total 30 pages
VS23S010C Datasheet
VS23S010C-L - 1 Megabit SPI SRAM
with Serial and Parallel Interfaces
and Integrated Video Display Controller
Features
Description
• Flexible 1.5V - 3.6V operating voltage
• 131,072 x 8-bit SRAM organization
• Serial Peripheral Interface (SPI) mode
0 compatible
– Byte, Page and Sequential modes
– Supports Single, Dual and Quad
I/O read and write
– Fast operation: the whole mem-
ory can be filled in 262158 or read
in 262159 cycles (Quad-I/O SPI,
Quad address mode)
– XHOLD and XWP pins
• 8-bit Parallel Interface (Simplified 8080
and NAND FLASH Type Interface)
– Sequential read and write in 4 byte
blocks
– Fast operation, the whole memory
can be filled or read in 131077 cy-
cles
• Integrated Video Display Controller with
Video DAC
– Supports NTSC and PAL video for-
mats
– Fully configurable by user
– 9-bit Video DAC and 8x Video PLL
• High operating frequencies
– Up to 36 MHz for SPI
The VLSI Solution VS23S010C-L is an easy-
to-use and versatile serial SRAM device. The
memory is accessed via an SPI compatible
serial bus. The device also contains Video
Display Controller, which can be configured
to continuously output analog video from the
memory array data to implement a video frame
buffer.
Alternatively, a 8-bit parallel interface can be
used to access the SRAM instead of the SPI.
To sum up, there are four separate operating
modes in VS23S010C-L:
• SPI Single, Dual, or Quad operation and
4 General Purpose I/O pins
• SPI Single, Dual, or Quad operation and
simultaneous Video Display Controller
• 8-bit Parallel Interface operation
• 8-bit Parallel Interface operation and si-
multaneous Video Display Controller
Applications
• Microcontroller RAM extension
• VoIP and internet data stream buffer
• Audio data buffer
• Video frame buffer
– Over 35 MHz for Video Display Con-
troller
1
– 15 MHz for 8-bit parallel interface
– (TBD) MHz for SRAM writes when
Video Display Controller enabled
• Active Low-power
– Read current 200 µA at 1 MHz (Sin-
gle I/O, SO=0, TA=+85◦C, VDD=3.3V)
SO/IO1
GND0
VideoOut #2
VideoOut #3
VideoOut #0
VideoOut #1
GND1
XWP/IO2
VXTALOUT
VXTALIN
XHOLD/IO3
SCLK
GND3
• Industrial temperature range
– -40◦C to + 85◦C
• Pb-Free and RoHS compliant
Figure 1: LQFP48 pin out (not to scale)
Version: 0.9 [Preliminary], 2015-01-16
1
1 Page VS23S010C Datasheet
Micro−controller
IO
IO
IO
IO
IO
IO
control
clock
data
data
data
data
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4 VS23S010
PIO5
PIO6
PIO7
XCSPAR
XRD
XWR
PGCLK
XRESET
MVBLK
VIDEOOUT
SPI Quad−I/O connection
IO
IO
IO
IO
Micro−controller
IO
to display
75 Ω
control
clock
data
data
clock
reset
control
analog video
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4 VS23S010
PIO5
PIO6
PIO7
XCSPAR
XRD
XWR
PGCLK
XRESET
MVBLK
VIDEOOUT
SPI connection (minimum configuration), video generator enabled
IO
IO
IO
IO
Micro−controller
IO
to display
control
clock
data
data
clock
reset
control
analog video
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4 VS23S010
PIO5
PIO6
PIO7
XCSPAR
CLKPAR
PGCLK
XRESET
MVBLK
VIDEOOUT
SPI connection (minimum configuration), video generator enabled, video buffer
Micro−controller
IO
IO
IO
IO
IO
IO
IO
to display
control
clock
data
data
data
data
clock
reset
control
analog video
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4 VS23S010
PIO5
PIO6
PIO7
XCSPAR
XRD
XWR
PGCLK
XRESET
MVBLK
VIDEOOUT
SPI Quad−I/O connection, video generator enabled, video buffer
Micro−controller
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
data
data
data
data
data
data
data
data
control
clock
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4 VS23S010
PIO5
PIO6
PIO7
XCSPAR
XRD
XWR
PGCLK
XRESET
MVBLK
VIDEOOUT
8−bit parallel interface (minimum configuration, one clock is enough)
Micro−controller
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
data
data
data
data
data
data
data
data
control
clock
clock
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4 VS23S010
PIO5
PIO6
PIO7
XCSPAR
XRD
XWR
PGCLK
XRESET
MVBLK
VIDEOOUT
8−bit parallel interface
Micro−controller
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
to display
control
clock
data
data
data
data
data
data
data
data
control
clock
clock
clock
reset
control
analog video
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4
PIO5
VS23S010
PIO6
PIO7
XCSPAR
XRD
XWR
PGCLK
XRESET
MVBLK
VIDEOOUT
8−bit parallel interface, video generator enabled, video buffer
(SPI for video generator control when 8−bit interface is not active)
Version: 0.9 [Preliminary], 2015-01-16
3
3Pages VS23S010C Datasheet
LIST OF FIGURES
List of Figures
1 LQFP48 pin out (not to scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 SPI or 8-bit parallel interface and Video Display Controller can be enabled at the
same time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 SPI Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 SPI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 XHOLD Timing, SPI and Dual-I/O Input Modes. Notice that internal address
counter does not increment, when XHOLD is low. . . . . . . . . . . . . . . . . . . 12
6 XHOLD Timing, SPI and Dual-I/O Output Modes. Notice that internal address
counter does not increment, when XHOLD is low. . . . . . . . . . . . . . . . . . . 13
7 XWP Timing, SPI and Dual-I/O Modes. Notice that internal address counter
increments, when XWP is low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8 XRESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9 8-bit Parallel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10 SOIC8 narrow package, compatible with standard pin out (not to scale). . . . . . 18
11 LQFP48 pin out (not to scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12 Connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13 Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14 SPI Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15 SPI Byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
16 SPI Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
17 SPI Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18 SPI Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
19 SPI sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
20 SPI sequential write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
21 One VS23S010 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
22 Two VS23S010s operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
23 Three VS23S010s operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
24 Four VS23S010s operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
25 SPI read in Multi-IC system consisting of four VS23S010C-Ls . . . . . . . . . . . 34
26 Video Display Controller block diagram . . . . . . . . . . . . . . . . . . . . . . . 36
27 Video picture parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
28 Switchable low-pass Y filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
29 Video mode SRAM organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
30 Index address organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
31 Protoline data organization, when whole line is protoline . . . . . . . . . . . . . . 43
32 Protoline data organization for a picture line (Note that the starting address is
formed differently than in previous picture) . . . . . . . . . . . . . . . . . . . . . . 43
33 Normal line data organization example . . . . . . . . . . . . . . . . . . . . . . . . 44
34 Normal line data organization example, UVSkip value 4 . . . . . . . . . . . . . . 44
35 Block move parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
36 Direct DAC data organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
37 Timing of on-chip reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
38 Interlaced PAL video frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . 49
39 PAL video line timing principle (timing tolerances not shown) . . . . . . . . . . . 50
40 Example of 8-Bit Parallel Interface Signals . . . . . . . . . . . . . . . . . . . . . . 53
41 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
42 SPI Dual-Output Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
43 SPI Dual-Output Read, Dual Address . . . . . . . . . . . . . . . . . . . . . . . . 57
Version: 0.9 [Preliminary], 2015-01-16
6
6 Page | |||
ページ | 合計 : 30 ページ | ||
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PDF ダウンロード | [ VS23S010C データシート.PDF ] |
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部品番号 | 部品説明 | メーカ |
VS23S010C | 1 Megabit SPI SRAM | VLSI |
VS23S010C-S | 1 Megabit SPI SRAM | VLSI |