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GC4116のメーカーはETCです、この部品の機能は「MULTI-STANDARD QUAD DUC CHIP」です。 |
部品番号 | GC4116 |
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部品説明 | MULTI-STANDARD QUAD DUC CHIP | ||
メーカ | ETC | ||
ロゴ | |||
このページの下部にプレビューとGC4116ダウンロード(pdfファイル)リンクがあります。 Total 57 pages
GRAYCHIP
DSP CHIPS AND SYSTEMS
2185 Park Blvd.,
(650) 323-2955
FAX (650) 323-0206
Palo Alto, CA 94306
GC4116
MULTI-STANDARD
QUAD DUC CHIP
DATA SHEET
REV 1.0
APRIL 27, 2001
This datasheet may be changed without notice.
Graychip reserves the right to make changes in circuit design and/or specifications at any time
without notice. The user is cautioned to verify that datasheets are current before placing orders.
Information provided by Graychip is believed to be accurate and reliable. No responsibility is assumed by
Graychip for its use, nor for any infringement of patents or other rights of third parties which may arise
from its use. No license is granted by implication or otherwise under any patent rights of Graychip.
© Graychip, Inc. All rights reserved 1999-2001
1 Page GC4116 MULTI-STANDARD QUAD DUC CHIP
CORPORATE OFFICES:
GRAYCHIP, Inc.
2185 Park Blvd.
Palo Alto, CA 94306
PHONE:
(650) 323-2955
FAX:
(650) 323-0206
WEB PAGE:
www.graychip.com
E-MAIL:
CONTACTING GRAYCHIP
DATA SHEET REV 1.0
© 1999−2001 GRAYCHIP,INC.
- ii -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
3Pages GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
1.0 KEY FEATURES
• Output rates up to 100 MSPS
• Four identical up-convert channels
• 16 bit real or complex inputs
• Four bit serial input ports, or memory mapped input
registers
• Serial interface controller simplifies interfacing with
ASICs or DSP chips
• Resampler circuit filters, pulse shapes and
resamples data to allow arbitrary input to output
sample rate conversion
• Interpolation factors of
32 to 5,792 in each channel
16 to 32 by combining two channels
• Independent frequency, phase and gain controls
• User programmable 63 tap input filter
• 0.02 Hz tuning resolution
• 115 dB Spur Free Dynamic Range
• 90 dB or more image rejection
• 0.07 dB gain resolution
• 0.05 dB peak to peak passband ripple
• The four channels are summed into a single output
signal
• 22 bit sum I/O path to merge outputs from multiple
GC4116 chips
• 8 to 22 bit 2’s complement or offset binary
output samples
• Accepts QPSK or QAM symbol data directly,
performs transmit (pulse shape) filtering
• Performs pulse shaping and phase
equalization for IS95 and CDMA2000
• Exceeds Damps, GSM, & IS95 requirements
• Supports up to two 4 Mbaud channels.
• Microprocessor interface for control
• Built in diagnostics
• Each GC4116 chip upconverts:
Four GSM, DAMPS, or 1X CDMA carriers, or
Two 3X CDMA2000 carriers, or
Two 3.84MB UMTS carriers
• Power consumption at 70 MHz, 2.5 volts:
84 mW per DAMPS channel
107 mW per GSM channel
305mW per 3.84MB UMTS channel
• Industrial temperature range (-40C to +85C)
• GC4016-PB 160 ball PBGA
(15mm by 15mm) package
• 3.3volt I/O voltage, 2.5volt core voltage
• JTAG Boundary Scan
2.0 BLOCK DIAGRAM
SUM IN
22 BITS
SINA, SFSA, SCKA
SINB, SFSB, SCKB
SINC, SFSC, SCKC
SIND, SFSD, SCKD
(CHANNEL INPUTS)
TCK
TMS
TDI
TDO
SIA
SIB
JTAG
BOUNDARY SCAN
LOGIC
SYNC COUNTER
AND
DIAGNOSTIC TEST
GENERATOR
SO
CK, CK2X
CLOCK DOUBLING
AND
DISTRIBUTION CIRCUIT
WRMODE
CONTROL INTERFACE
CE WR RD A[0:4] C[0:7]
SERIAL
INPUTS
INPUT
AND GAIN
PARALLEL
INPUTS
CHANNEL A
63 TAP
PROGRAMMABLE
INTERPOLATE
BY 2 FILTER
(PFIR)
31 TAP
INTERPOLATE
BY 2 FILTER
(CFIR)
INTERPOLATE
BY 8 TO 2K
FILTER
(CIC)
CHANNEL B
63 TAP
PROGRAMMABLE
INTERPOLATE
BY 2 FILTER
(PFIR)
31 TAP
INTERPOLATE
BY 2 FILTER
(CFIR)
TUNING
FREQUENCY
PHASE
OFFSET
SINE/
COSINE
GENERATOR
INTERPOLATE
BY 8 TO 2K
FILTER
(CIC)
CHANNEL C
63 TAP
PROGRAMMABLE
INTERPOLATE
BY 2 FILTER
(PFIR)
31 TAP
INTERPOLATE
BY 2 FILTER
(CFIR)
TUNING
FREQUENCY
PHASE
OFFSET
SINE/
COSINE
GENERATOR
INTERPOLATE
BY 8 TO 2K
FILTER
(CIC)
CHANNEL D
63 TAP
PROGRAMMABLE
INTERPOLATE
BY 2 FILTER
(PFIR)
31 TAP
INTERPOLATE
BY 2 FILTER
(CFIR)
TUNING
FREQUENCY
PHASE
OFFSET
SINE/
COSINE
GENERATOR
INTERPOLATE
BY 8 TO 2K
FILTER
(CIC)
CHREQ
TUNING
FREQUENCY
PHASE
OFFSET
SINE/
COSINE
GENERATOR
SUM OUT
(8 to 22 BITS)
DIVIDE
BY 16
SCSTART
RINA, RFSA, RCKA
RINB, RFSB, RCKB
RINC, RFSC, RCKC
RIND, RFSD, RCKD
RSTART
SERIAL
CONTROLLER
FOUR CHANNEL
RESAMPLER
SCFSA
SCFSB
SCFSC
SCFSD
SCCK0, SCCK1
ROUTA
ROUTB
ROUTC
ROUTD
ROFS0, ROFS1
ROCK0, ROCK1
RREQ
Figure 1. GC4116 Block Diagram
© 1999−2001 GRAYCHIP,INC.
-1-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
6 Page | |||
ページ | 合計 : 57 ページ | ||
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PDF ダウンロード | [ GC4116 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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