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GS72116AU-10I の電気的特性と機能

GS72116AU-10IのメーカーはETCです、この部品の機能は「128K x 16 2Mb Asynchronous SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS72116AU-10I
部品説明 128K x 16 2Mb Asynchronous SRAM
メーカ ETC
ロゴ ETC ロゴ 




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GS72116AU-10I Datasheet, GS72116AU-10I PDF,ピン配置, 機能
GS72116ATP/J/T/U
SOJ, TSOP, FP-BGA, TQFP
128K x 16
Commercial Temp
Industrial Temp
2Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: 40° to 85°C
• Package line up
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
T: 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a sin-
gle 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
SOJ 128K x 16-Pin Configuration
A4 1
A3 2
A2 3
A1 4
A0 5
Top view
CE 6
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VDD 11
44-pin
VSS 12
DQ5 13
SOJ
DQ6 14
DQ7 15
DQ8 16
WE 17
A15 18
A14 19
A13 20
A12 21
A16 22
Package J
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ16
DQ15
DQ14
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
Pin Descriptions
Symbol
A0A16
DQ1DQ16
CE
LB
UB
WE
OE
VDD
VSS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
Rev: 1.04a 10/2002
1/18
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.

1 Page





GS72116AU-10I pdf, ピン配列
Block Diagram
TSOP-II 128K x 16-Pin Configuration
A4 1
A3 2
A2 3
A1 4
Top view
A0 5
CE 6
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VDD 11
44-pin
VSS
DQ5
12
13
TSOP II
DQ6 14
DQ7 15
DQ8 16
WE 17
A15 18
A14 19
A13 20
A12 21
A16 22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 DQ16
37 DQ15
36 DQ14
35
34
33
32
31
DQ13
VSS
VDD
DQ12
DQ11
30 DQ10
29 DQ9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
Package TP
A0 Row
Decoder
Address
Input
Buffer
A16
CE
WE
OE
Control
UB _____
LB _____
Memory Array
Column
Decoder
I/O Buffer
DQ1 DQ16
GS72116ATP/J/T/U
Rev: 1.04a 10/2002
3/18
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.


3Pages


GS72116AU-10I 電子部品, 半導体
GS72116ATP/J/T/U
Power Supply Currents
Parameter
Operating
Supply
Current
Standby
Current
Standby
Current
Symbol
IDD (max)
ISB1
(max)
ISB2
(max)
Test Conditions
CE VIL
All other inputs
VIH or VIL
Min. cycle time
IOUT = 0 mA
CE VIH
All other inputs
VIH or VIL
Min. cycle time
CE VDD 0.2 V
All other inputs
VDD 0.2 V or
0.2 V
0 to 70°C
7 ns 8 ns 10 ns
145 mA 125 mA 100 mA
25 mA 20 mA 20 mA
5 mA
12 ns
85 mA
15 mA
40 to 85°C
7 ns 8 ns 10 ns
150 mA 130 mA 105 mA
30 mA 25 mA 25 mA
10 mA
12 ns
90 mA
20 mA
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
Input rise time
Input fall time
Input reference level
Output reference level
Output load
VIH = 2.4 V
VIL = 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
1.4 V
Fig. 1& 2
Note:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Output Load 1
DQ
5030pF1
VT = 1.4 V
Output Load 2
3.3 V
DQ 589
5pF1 434
Rev: 1.04a 10/2002
6/18
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.

6 Page



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部品番号部品説明メーカ
GS72116AU-10

128K x 16 2Mb Asynchronous SRAM

ETC
ETC
GS72116AU-10I

128K x 16 2Mb Asynchronous SRAM

ETC
ETC


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