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GS72108TP-10 の電気的特性と機能

GS72108TP-10のメーカーはETCです、この部品の機能は「256K x 8 2Mb Asynchronous SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS72108TP-10
部品説明 256K x 8 2Mb Asynchronous SRAM
メーカ ETC
ロゴ ETC ロゴ 




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GS72108TP-10 Datasheet, GS72108TP-10 PDF,ピン配置, 機能
GS72108TP/J
SOJ, TSOP
Commercial Temp
Industrial Temp
Features
256K x 8
2Mb Asynchronous SRAM
8, 10, 12, 15 ns
3.3 V VDD
Center VDD and VSS
SOJ 256K x 8-Pin Configuration
• Fast access time: 8, 10, 12, 15 ns
• CMOS low power operation: 150/125/110/90 mA at
minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 36-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
Description
The GS72108 is a high speed CMOS Static RAM organized as
262,144 words by 8 bits. Static design eliminates the need for
external clocks or timing strobes. The GS operates on a single
3.3 V power supply and all inputs and outputs are TTL-com-
patible. The GS72108 is available in 400 mil SOJ and 400 mil
TSOP Type-II packages.
Pin Descriptions
Symbol
A0A17
DQ1DQ8
CE
WE
OE
VDD
VSS
NC
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
DQ1 7
DQ2 8
VDD 9
VSS 10
DQ3 11
DQ4 12
WE 13
A17 14
A16 15
A15 16
A14 17
A13 18
36-pin
400 mil SOJ
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A5
A6
A7
A8
OE
DQ8
DQ7
VSS
VDD
DQ6
DQ5
A9
A10
A11
A12
NC
NC
Rev: 1.08 7/2002
1/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

1 Page





GS72108TP-10 pdf, ピン配列
Truth Table
CE OE
HX
LL
LX
LH
Note: X: “H” or “L”
WE
X
H
L
H
DQ1 to DQ8
Not Selected
Read
Write
High Z
GS72108TP/J
VDD Current
ISB1, ISB2
IDD
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
Input Voltage
Output Voltage
Allowable power dissipation
Storage temperature
VDD
VIN
VOUT
PD
TSTG
0.5 to +4.6
0.5 to VDD +0.5
(4.6 V max.)
0.5 to VDD +0.5
(4.6 V max.)
0.7
55 to 150
V
V
V
W
oC
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Rev: 1.08 7/2002
3/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.


3Pages


GS72108TP-10 電子部品, 半導体
AC Characteristics
GS72108TP/J
Read Cycle
Parameter
-8 -10 -12 -15
Symbol
Unit
Min Max Min Max Min Max Min Max
Read cycle time
Address access time
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
tRC 8 10 12 15 ns
tAA 8 10 12 15 ns
tAC 8 10 12 15 ns
tOE 3.5 4 5 6 ns
tOH 3 3 3 3 ns
tLZ* 3 3 3 3 ns
tOLZ* 0 0 0 0 ns
tHZ* 4 5 6 7 ns
tOHZ* 3.5 4 5 6 ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH
Address
Data Out
tOH
Previous Data
tRC
tAA
Data valid
Rev: 1.08 7/2002
6/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
GS72108TP-10

256K x 8 2Mb Asynchronous SRAM

ETC
ETC
GS72108TP-10I

256K x 8 2Mb Asynchronous SRAM

ETC
ETC
GS72108TP-12

256K x 8 2Mb Asynchronous SRAM

ETC
ETC
GS72108TP-12I

256K x 8 2Mb Asynchronous SRAM

ETC
ETC


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