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GS7005-CTT の電気的特性と機能

GS7005-CTTのメーカーはETCです、この部品の機能は「Complete Serial Digital Video Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS7005-CTT
部品説明 Complete Serial Digital Video Receiver
メーカ ETC
ロゴ ETC ロゴ 




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GS7005-CTT Datasheet, GS7005-CTT PDF,ピン配置, 機能
PRO-LINX GS7005
Complete Serial Digital Video Receiver
FEATURES
• SMPTE 259M-C compliant
• fully integrated 270 Mb/s SDI receiver
• integrated cable equalization (100m Belden 8281 typical)
• low power consumption (750mW typical)
• operates from 0°C to 85°C
• small footprint with minimal external components
• Lock and Carrier Detect output indications
• H timing signal output
• SMPTE descrambler and NRZI decoder may be
disabled for DVB - ASI applications
• ease of design use and adjustment free operation
APPLICATIONS
Limited space, low power SMPTE 259M-C or generic
270Mb/s serial to parallel interfaces; DVB-ASI 270Mb/s
receive interface; broadcast quality uncompressed video
interface for industrial and professional video equipment
such as video editing workstations.
DATA SHEET
DESCRIPTION
The GS7005 is a BiCMOS integrated circuit capable of
operating as a complete 270Mb/s Serial Digital Video
receiver. The GS7005 provides a complete serial digital
video receive solution while consuming only 750mW.
The serial data input accepts SMPTE 259M-C compliant
signals. An on-chip by-passable equalizer typically pro-
vides 100m of co-axial cable equalization. The clock
recovery is performed on chip with minimal external
components. The incoming serial data is decoded using an
NRZI decoder and SMPTE descrambler to provide SMPTE
125M compliant 27Mb/s parallel data outputs and clock.
ORDERING INFORMATION
PART NUMBER
PACKAGE
GS7005 - CQT
52 pin MQFP
GS7005 - CTT
52 pin MQFP Tape
TEMPERATURE
0°C to 85°C
0°C to 85°C
LOCK
CD
SDI
SDI
C1 C2
SIGNAL
LOCK
DETECT
EQUALIZER
SLICER
PLL
MUX
NRZI
DECODER
f/10
TRS
DETECTOR
DESCRAMBLER
PCLKOUT
H
S to P
DOUT[9:0}
10
EQ SMPTE
BLOCK DIAGRAM
Revision Date: January 2001
Document No. 522 - 14 - 06
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com

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GS7005-CTT pdf, ピン配列
AC ELECTRICAL CHARACTERISTICS
VCC = 5V, TA = 25°C, unless otherwise specified in ‘conditions’
Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, ƒPCLK = 27MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTE
S
TEST
LEVEL
Parallel Data - Rise/Fall Time
tR/F_DOUT
CL = 20pF
1.0 - 6.0 ns 1 4, 7
PCLK Rising Edge to DOUT(N) Centre
tD
- - ±5 ns 2, 3 4, 7
PCLK Rise/Fall Time
Input Return Loss
tR/F_PCLKOUT
CL = 20pF
0.5 - 3.0 ns 1 4, 7
LOSSIN
75match
- 17 - dB
5MHz to 270MHz
7
Asynchronous Lock Time
tLOCK_ASYNC
- - 250 ms 4
1
Synchronous Lock Time
tLOCK_SYNC
- - 10 µs 5
1
Input Jitter Tolerance
tJ_SI
Pathological Input
- 0.35
-
U.I.
6
7
Output PCLK Jitter
tJ_PCLKOUT
Pseudorandom
Input
- 800
- ps p-p
1
Pathological Input
- 1000
- ps p-p 6
7
Error Free Cable Length
Pseudorandom
Input
- 100
-
m
7
Pathological Input 75 100
-
m 6, 7
1
NOTES
1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the
specified value.
2. Refer also to Figure 10.
3. This is the time difference between the rising edge of PCLKOUT and the centre of the bit period.
4. This is the time delay between a valid serial TRS signal on the input to the moment valid data appears on the parallel outputs.
5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE
RP168-1993. The two streams may be 180° out of phase with respect to one another, but pixel aligned.
6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3.
7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75connections. The MIN
value is fully tested and the TYP value is based on using the EB7005 Evaluation Board.
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
GENNUM CORPORATION
3
522 - 14 - 06


3Pages


GS7005-CTT 電子部品, 半導体
INPUT / OUTPUT CIRCUITS
ESD
IN
VDD
TO INTERNAL
STRUCTURES
GND
Fig. 2 SDI, SDI
VDD
TO INTERNAL
STRUCTURES
ESD
OUT
GND
Fig. 3 DOUT[9:0], H, LOCK, CD, PCLKOUT
ESD
TTL-IN
VDD
TO INTERNAL
STRUCTURES
GENNUM CORPORATION
GND
Fig. 4 EQ, SMPTE
6
522 - 14 - 06

6 Page



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部品番号部品説明メーカ
GS7005-CTT

Complete Serial Digital Video Receiver

ETC
ETC


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