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GP4020 の電気的特性と機能

GP4020のメーカーはZarlink Semiconductor Incです、この部品の機能は「GPS Receiver Baseband Processor」です。


製品の詳細 ( Datasheet PDF )

部品番号 GP4020
部品説明 GPS Receiver Baseband Processor
メーカ Zarlink Semiconductor Inc
ロゴ Zarlink Semiconductor Inc ロゴ 




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GP4020 Datasheet, GP4020 PDF,ピン配置, 機能
GP4020
GPS Receiver Baseband Processor
Features
• Complete GPS correlator and Firefly MF1
microcontroller core
• ARM 7TDMITM (Thumb®) Microprocessor, with JTAG
ICEBreakerTM Debug Interface
• Fully Configurable External Data Bus
• 12 Fully Independent Correlation Channels
• Low Voltage Operation: 3·3V
• Low Current Power–Down Mode
• 1PPS UTC Aligned Timing Output
• Dual UART
• 3-wire BµILD Serial Input/Output (BSIO) Interface
• 8 General Purpose Input/Output (GPIO) Lines
• Boot ROM, allowing Software Upload via UART
• 8K Bytes Internal SRAM
• Compatible with GP2015 and GP2010 RF Front Ends
Applications
GPS Navigation Systems
GPS Geodetic Receivers
Time Transfer Receivers
Automatic Vehicle Location (AVL)
E911 Emergency Positioning
Related Products
Part Description
GP2015
GP2010
GPS Receiver RF Front End
(TQFP 48 package)
GPS Receiver RF Front End
(PQFP 44 package)
Data sheet
DS4374
DS4056
DS5134
ISSUE 4.4
May 2002
Ordering Information
GP4020/IG/GQ1N (trays)
GP4020/IG/GQ1Q (tape and reel, 1000 units per reel)
The GP4020 is available in a 100 pin PQFP package in
Industrial (-40°C to +85°C) grade. The ordering code is
standard for screened devices
Description
The GP4020 is a complete digital baseband processor
for a Global Positioning System (GPS) receiver. It
combines the 12-channel correlator function of the
GP2021 with an advanced ARM7TDMI (Thumb)
microprocessor to achieve a higher level of integration,
reduced system cost, reduced power consumption and
added functionality. The GP4020 complements the
GP2015 and GP2010 C/A code RF downconverters
available from Zarlink Semiconductor.
The correlator section contains 12 identical tracking
module blocks, one for each channel. Each channel
contains all the components necessary for acquiring
and tracking the received signal, and also contains
other functional blocks, which are used to produce part
of the measurement data set. Individual channels may
be deactivated for systems not requiring full 12-channel
operation and thus allowing for reduced power
consumption and processor loading.
The microprocessor section contains the Firefly MF1
microcontroller core, which includes an ARM7TDMI
with a Thumb instruction de-compressor plus the Firefly
BµILD module. Also included are a second UART,
BµILD Serial I/O, General I/O and Watchdog functions.
Absolute Maximum Ratings
Supply voltage (VDD) from ground (GND)
Bias for 5V inputs
Input voltage (any input pin)
Output voltage (any output pin)
Storage temperature
Static discharge (HBM)*
-0·5V to +5·0V
+7·0V max.
GND-0·5V to VDD+0·5V
GND-0·5V to VDD+0·5V
-55°C to +150°C
2kV
*Mil Std 883 Human Body Model = discharge from 100pF through
1500between any 2 pins
Manufactured under licence from ARM Ltd
ARM and the ARM logo are trademarks of Advanced RISC Machines Ltd

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GP4020 pdf, ピン配列
GP4020
76 50
100
1 25
Figure 2 - Pin connections (top view)
QPA100
Pin No. Signal Name
Type
Associated
circuit block
Description
Notes
1 SADD[0]
I/O
MPC
System Address bit 0
2 SADD[1]
3 SADD[2]
4 SADD[3]
5 SADD[4]
6 SADD[5]
7 GNDPWR
8 SADD[6]
9 SADD[7]
10 VDD PWR
11 NSCS[0]
12 NSCS[1]
13 NSCS[2A]
14 SADD[19]
15 SDATA[0]
16 SDATA[1]
17 SDATA[2]
18 SDATA[3]
19 GNDPWR
20 SDATA[4]
21 SDATA[5]
22 VDD PWR
23 SDATA[6]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
System Address bit 1
System Address bit 2
System Address bit 3
System Address bit 4
System Address bit 5
System Address bit 6
System Address bit 7
System Chip Select 0 - Active Low
System Chip Select 1 - Active Low
System Chip Select 2A - Active Low
System Address bit 19
System Data bit 01
System Data bit 11
System Data bit 21
System Data bit 31
System Data bit 41
System Data bit 51
System Data bit 61
1
1
1
Table 1 - Pin descriptions
Cont
All VDD and GND pins must be connected to ensure reliable operation. Any unused input pins must be tied either
high or low; no inputs should be left unconnected.
3


3Pages


GP4020 電子部品, 半導体
GP4020
Pin No. Signal name
Type
Associated
circuit block
Description
Notes
89 TMS/bdiag[3]/XCon
90 NTRST
91 GPI0[7]/PLLDT1
92 GPIO[6]
93 GPIO[5]/DISCOP
94 GND
95 GPIO[4]/DISCIP1
96 GPIO[3]/BSIO_SS[1]
97 GPIO[2]/BSIO_SS[0]
98 VDD
99 GPIO[1]/BSIO_DATA
100 GPIO[0]/BSIO_CLK
I/O
I
I/O
I/O
I/O
PWR
I/O
I/O
I/O
PWR
I/O
I/O
JTAG/SSM
JTAG/SSM
GPIO/SCG PLL
GPIO
GPIO/CORR
JTAG Test Mode Select/SSM Diagnostic
broadcast debug output bdiag[3]/System test
control input XCon.
JTAG interface Reset or SSM debug interface
multiplex (pins 86, 87, 88 and 89).
General Purpose Input/Output 7. Can be
multiplexed to SCG PLL Digital Test Output
(PLLDT1).
General Purpose Input/Output 6.
General Purpose Input/Output 5. Can be
multiplexed to DISCOP discrete output from
correlator.
GPIO/CORR
GPIO/BSIO
GPIO/BSIO
General Purpose Input/Output 4. Also directly
connectstoDISCIP1onthe12-channelcorrelator.
General Purpose Input/Output 3. Can be
multiplexed to BSIO Slave Select[1].
General Purpose Input/Output 2. Can be
multiplexed to BSIO Slave Select[0].
GPIO/BSIO
GPIO/BSIO
General Purpose Input/Output 1. Can be
multiplexed to BSIO Data Input/Output.
General Purpose Input/Output pin 0. Can be
multiplexed to BSIO_CLK output.
6
6
3
3
3
3
3
3
3
3
Table 1 - Pin descriptions (continued)
NOTES
1. High impedance is achieved on pins 11 to 18, 20, 21, 23 to 29, 31, 32, 34 to 37 when either:
(a) Data is not being written from GP4020.
(b) POWER_GOOD (pin 64) is low.
(c) Bit 1 (RF_PD) of POW_CNTL register is high.
(d) Bit 10 (RF_SLEEP) of POW_CNTL register is high.
2. NSUB (pin 52) is the Upper Byte select output from the Memory Peripheral Controller, when single chip 16-bit
memories with NUB and NLB inputs are used. NSUB maps to NUB and address line SADD[0] to NLB.
3. Input is tolerant to being driven with a +5V HIGH level, as well as +3·3V HIGH nominal level.
4. Both CLK_T (pin 58) and CLK_I (pin 59) should not have an external DC bias of GREATER than +1·7V . Direct
connection from a GP2010/GP2015 RF front end is NOT possible, without bias-shift circuit (Figure 3).
5. TEST (pin 67) and TESTMODE (pin 74) are used together to set up manufacturing test modes for the GP4020,
as shown in Table 2 (0 = GND, 1 = VDD).
TEST TESTMODE
(pin 67) (pin 74)
Test function
0 0 Normal operation
1 0 Firefly Macrocell test mode
0 1 Firefly System test mode
1 1 UIM logic test mode
Table 2 - Test mode truth table
Details of ALL test modes are covered in section 2.10 of the Zarlink Semiconductor Firefly MF1 Core Design
Manual.
6

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