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PDF GP2015 Data sheet ( Hoja de datos )
| Número de pieza | GP2015 | |
| Descripción | GPS Receiver RF Front End | |
| Fabricantes | Mitel Networks Corporation | |
| Logotipo |  |
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GP2015
GPS Receiver RF Front End
Supersedes edition in August 1996 Global Positioning Products Handbook, HB4305-1.0
DS4374 - 2.4 October 1996
The GP2015 is a small format RF Front-end for Global
Positioning System (GPS) receivers. Equivalent in
performance to the GP2010 but in a TQFP package, this
product is suited for size-critical applications as the RF area
can be reduced by a factor of two to three using miniature
surface mount passive components The GP2015 is designed
to operate from either 3 or 5 Volt supplies.
The input to the device is the L1 (1575.42MHz) Coarse-
Acquisition (C/A) code Global Positioning signal from an
antenna (via a low-noise pre-amplifier). The output is 2-bit
quantised for subsequent signal processing in the digital
domain. The GP2015 contains an on-chip synthesiser, mixers,
AGC and a quantiser which provides Sign and Magnitude
digital outputs. A minimum of external components is required
to make a complete GPS front-end.
The device has been designed to operate with the GP2021
12-channel Global Positioning Correlator, and DW9255 SAW
filter, both also available from Mitel Semiconductor.
FEATURES
s Ultra miniature TQFP package
s Low Voltage Operation (3V - 5V)
s Low Power - 200mW typ. (3V supply)
s C/A Code Compatible
s On-chip PLL Including Complete VCO
s Triple Conversion Receiver
s 48-Lead Surface Mount Quad Flat-Pack Package
s Sign and Magnitude Digital Outputs
s Compatible with GP2021 CMOS Correlator
APPLICATIONS
s C/A Code Global Positioning by Satellite Receivers
s Time Standards
s Navigation
s Surveying
ORDERING INFORMATION
The GP2015 is available in 48 pin TQFP package to
Industrial (-40°C to +85°C) grade.
ORDERING CODE
GP2015 IG FP1R Industrial - Plastic 48-pin TQFP
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 21
41 20
42 GP2015 19
43 18
44 17
45 16
46 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
FP48
Pin Name
1 IF Output
2 PLL Filter 1
3 PLL Filter 2
4 VEE (OSC)
5 VCC (OSC)
6 VEE (OSC)
7 VEE (REG)
8 PRef
9 PReset
10 VEE (IO)
11 CLK
12 N/C
13 N/C
14 MAG
15 SIGN
16 OPCIK-
17 OPCIK+
18 VDD (IO)
19 PDN
20 TEST
21 LD
22 VEE (DIG)
23 AGC -
24 AGC +
Pin Name
25 N/C
26 VCC (DIG)
27 REF 2
28 REF 1
29 VCC (RF)
30 VEE (RF)
31 VEE (RF)
32 RF Input
33 VEE (RF)
34 VEE (RF)
35 VCC (RF)
36 N/C
37 O/P 1-
38 O/P 1+
39 VCC (2)
40 I/P 2-
41 I/P 2+
42 VEE (IF)
43 VEE (IF)
44 O/P 2-
45 O/P 2+
46 VCC (3)
47 I/P 3-
48 I/P 3+
Fig. 1 Pin connections - top view
RELATED PRODUCTS AND PUBLICATIONS
Part
Description
Data
Reference
DW9255
GP2021
GP2010
GP2015
GPSBuilder-2
GPSBuilder-2.1
35.42MHz SAW Filter
Twelve-Channel Correlator
GPS receiver RF Front-end
Design with the GP2015
Twelve-Channel GPS receiver
development system
Twelve-Channel GPS development
system
DS3861
DS4057
DS4056
AN4533
DS4004
DS4537
1 page  
GP2015
Characteristic
Value
Units
Min. Typ. Max.
Conditions
VCO Maximum Lock Frequency
VCO Minimum Lock Frequency
VCO regulator output voltage
VCO Gain
Phase Detector Gain
10MHz Reference Input
10MHz Reference Input Impedance
PLL Lockup Time
PLL Loop Gain
DIGITAL INTERFACES
Sample Clock, Power Down,
Test Inputs.
VIH
VIL
Input Current High IIH
Input Current Low IIL
Sign/Mag Outputs
VOH
VOL
Sample Clock to Sign/Mag Delay
40MHz Clock Output
High Level (VOH)
Low Level (VOL)
Output (differential)
Duty Cycle
LD (PLL Lock)/PReset Outputs
Low Level (VOL)
High Level (VOH)
Power-on Reset comparator input
Power Reset Reference Level
Power Reset Reference Input Current
1414
3
50
0.1
MHz
1386 MHz
3.3 3.5
V (Note 4)
150 240 MHz/V
5.3 V/rad (Note 7)
0.6 1.2 V pk-pk Pin 27
5 kΩ (Note 11)
6 ms From Power up (Note 7)
150 dB (Note 7)
2
0
-300
VDD-1
VDD
0.5
10
0.5
20
Pins 11, 19, 20
V
V
µA VIH = VDD
µA VIL = VEE
Pins 15, 14
V IO = -0.5mA
V IO = 0.5mA
ns CL = 15pF, RL = 15kΩ (Note 7)
VDD-1.25 VDD-1 VDD-0.8 V
VOH-0.1
V
220 mV p-p
43 %
Pins 16 & 17
(Note 5)
CL = 15pF (GND) (Note 7)
CL = 5pF (Diff) (Note 7)
(Note 7)
0.2 0.5
VDD-1 VDD
Pins 21 and 9
V IO = 0.5mA
V IO = -10µA
Pin 8
1.1 1.35 V
-10 10 µA
Notes On Electrical Characteristics:- All RF measurements are made with appropriate matching to the input or output
impedances, such as balun transformers, and levels refer to matched 50ohm ports (see figure 3 for test circuit)
1. RF input impedance (series) without input matching components connected - expressed as Real impedance with reactive
inductor value. Measured at 1575.42MHz.
2. Input matched to 50ohm, output loaded wlth 600ohm differential
3. Maximum Stage 3 input signal amplitude for correct AGC operation = 20mV rms.
4. VCO regulator voltage measured with respect to Vcc (OSC) - pin 5.
5. The OPCLK outputs are differential and are referenced to VDD.
6. Minimum gain requirement expressions:
-7dBm < -174dBm/Hz + 19dB + G1 + G2 + G3 - 21dB + 63dB
where -7dBm = typical IF Output level with AGC active (equivalent to 100mV rms)
-174dBm/Hz = background noise level at RF input
19dB = sum of LNA gain and noise figure
-21dB = total loss in 175MHz and 35MHz filters
63dB = summation of noise over a 2MHz bandwidth
Rearranging the above expression gives G1 + G2 + G3 > 106dB.
7. This parameter is not production tested.
8. This impedance is toleranced at +/-30% and is not production tested.
9. Roll off occurs in on-chip capacitive coupling IF Output to input of ADC circuit. Not measurable at IF Output.
10. CW input on pins 47 & 48 of 35.42MHz at 7mV rms.
11. This input impedance applies to the typical input level. The impedance is level dependent and is not tested or guaranteed.
5
5 Page 
GP2015
Ref 2
(27)
GP2015
(28) NC
Ref 1
47nF
RA
RB
10.000MHz
TCXO
RA & RB SET TO REDUCE TCXO
O/P TO 0.5V P-P.
Fig. 6 TCXO Reference connections
3V
V CCOSC
(5)
GP2015
(4)
V EEOSC
(6)
(7)
V EEREG
0V
No VCO Regulator needed
5V
V CCOSC
(5)
100nF
GP2015
(4)
V EEOSC
(6)
(7)
V EEREG
0V
Using VCO regulator with Vcc > +4.0V
Fig. 7 VCO power-supply connections
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet GP2015.PDF ] | |
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