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GP1020CGGPKR の電気的特性と機能

GP1020CGGPKRのメーカーはZarlink Semiconductor Incです、この部品の機能は「SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS」です。


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部品番号 GP1020CGGPKR
部品説明 SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS
メーカ Zarlink Semiconductor Inc
ロゴ Zarlink Semiconductor Inc ロゴ 




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GP1020CGGPKR Datasheet, GP1020CGGPKR PDF,ピン配置, 機能
FEBRUARY 1994
DS3605-2.2
GP1020
SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT
FOR GPS OR GLONASS RECEIVERS
The GP1020 is a six-channel CMOS digital correlator which
has been designed to work with the GP1010 L1-channel down-
converter or other integrated circuits, and may be used to acquire
and track the GPS C/A code or the GLONASS signals.
For each of the six channels the GP1020 includes independ-
ent digital down-conversion to baseband, C/A code generation,
correlation, and accumulate-and-dump registers.
The GP1020 interfaces with a microprocessor via a 16-bit
data bus to control the acquisition and tracking processes using
the various registers on the chip.
FEATURES
s Six Fully Independent Correlation Channels
s Switchable to Receive GPS or GLONASS Codes
s Input Multiplexer for Multiple GPS Front-Ends – Allows
Antenna Diversity
s Input Multiplexer for GLONASS Multiple (Separate
Channels) Front-Ends
s Digital Interface Compatible with Most 16 or 32-Bit
Microprocessors
s Fully Compatible with GP1010 GPS Receiver Front-End
s Sideways Stackable to give Multiples of Six Channels
s 120-pin Plastic Quad Flatpack
s Power Dissipation Less Than 500mW
APPLICATIONS
s GPS or GLONASS Navigation Systems
s High Integrity Combined Receivers
s GPS Geodetic Receivers
s GPS Time Reference
ORDERING INFORMATION
The GP1020 is available in 120-pin Quad Flatpacks (Gullwing
formed leads) in both Commercial (0°C to 170°C) and Industrial
(240°C to 185°C) grades. The ordering codes below are for
standard screened devices.
ORDERING CODES
GP1020 CG GPKR Commercial - Plastic 120-pin QFP (GP120)
GP1020 IG GPKR Industrial - Plastic 120-pin QFP (GP120)
90
91
61
60
GP1020
120 31
1 30 GP120
Fig 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
These are not the operating conditions, but are the absolute
limits which if exceeded, even momentarily, may cause perma-
nent damage. To ensure sustained correct operation the device
should be used within the limits given under Electrical Character-
istics.
Supply voltage (VDD) from ground (VSS):
20·3V to16·0 V
Input voltage (any input pin):
VSS20·3V to VDD10·3 V
Output voltage (any output pin):
VSS20·3V to VDD10·3 V
Storage temperature:
255°C to 1125°C
RELATED PRODUCTS
Part
Description
DW9255 35·42MHz SAW Filter
GP1010 GPS Receiver Front-End
Datasheet
Reference
DS3861
DS3076

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GP1020CGGPKR pdf, ピン配列
PIN DESCRIPTIONS (See Application Notes, p. 41)
All VSS and all VDD pins must be used in order to ensure
reliable operation. Several pins, such as Satellite Inputs 2 to
9 Sign and Magnitudes are also used for device testing, but
only as a secondary function.
Pin
No.
Signal
name
Type
Description
1 A7
I Register Address, bit 7
2 A8
I Register Address, bit 8
3 MASTER/
I Master or slave mode select
SLAVE
4 TSCAN
I Scan Test mode select
5 TCKS
I Test Clock select
6 TDI1
I Serial Test Data Input
7 MASTER
I Master Reset (active low)
RESET
8 MOT/INTEL I Motorola (hi) or Intel (lo) bus select
9 CS
I Chip Select (active low) for bus
10 VSS
11 VDD
12 WEN
2 Ground
1 Positive supply
I Bus control - see note 1
13 RW
I Bus control - see note 1
14 TMS2
I Test Mode Select 2
15 TMS1
I Test Mode Select 1
16 TMAG
O Test PRN Pattern Magnitude o/p
17 TSIGN
O Test PRN Pattern Sign output
18 MAG2
I/O Satellite Input 2, Magnitude
19 100/219kHz O Programmable Interrupt Timer clock
20 VDD
21 VSS
22 INTOUT
1 Positive supply
2 Ground
O Interrupt out to microprocessor
23 SIGN2
I/O Satellite Input 2, Sign
24 MAG3
I/O Satellite Input 3, Magnitude
25 SIGN3
I/O Satellite Input 3, Sign
26 MAG4
I/O Satellite Input 4, Magnitude
27 SIGN4
I/O Satellite Input 4, Sign
28 MAG5
I/O Satellite Input 5, Magnitude
29 SIGN5
I/O Satellite Input 5, Sign
30 MAG6
I/O Satellite Input 6, Magnitude
31 SIGN6
I/O Satellite Input 6, Sign
32 MAG7
I/O Satellite Input 7, Magnitude
33 SIGN7
I/O Satellite Input 7, Sign
34 MAG8
I/O Satellite Input 8, Magnitude
35 SIGN8
I/O Satellite Input 8, Sign
36 MAG9
I/O Satellite Input 9, Magnitude
37 SIGN9
I/O Satellite Input 9, Sign
38 MAG1
I/O Satellite Input 1, Magnitude
39 SIGN1
I/O Satellite Input 1, Sign
40 VSS
41 VDD
42 MAG0
2 Ground
1 Positive supply
I Satellite Input 0, Magnitude
43 SIGN0
I Satellite Input 0, Sign
44 SAMPCLK
O Sampling clock to down-converter
45 VDD
1 Positive supply
46 MASTERCLK I 40MHz Master Clock
47 VSS
48 Bias
2 Ground
O Bias for MASTERCLK in 600mV
AC-coupled mode
49 VSS
50 VDD
51 VSS
52 CLKSEL
2 Ground
1 Positive supply
2 Ground
I Sets 100/219kHz to 100or 219kHz
53 PLLLOCKIN I PLLlockstatusfromdown-converter
54 BITECNTL O BITE control to down-converter
55 GLONASSBIT I I/P to monitor GLONASS front-end
56 SLAVECLK I/O 20MHz clock from Master to slave
57 INTIN
I Interrupt to slave to sync to Master
58 TCK1
I/O Test Clock 1
59 TCK2
I/O Test Clock 2
60 TCK3
I/O Test Clock 3
61 TCK4
I/O Test Clock 4
62 TCK5
I/O Test Clock 5
63 TCK6
I/O Test Clock 6
64 TCK7
I/O Test Clock 7
65 TCK8
I Test Clock 8
GP1020
Pin
No.
Signal
name
Type
Description
66 TICIN
I TIC input to slave
67 TICOUT
O TIC output from Master
68 D0
I/O Data Bus, bit 0
69 D1
I/O Data Bus, bit 1
70 VSS
71 VDD
72 D2
2 Ground
1 Positive supply
I/O Data Bus, bit 2
73 D3
I/O Data Bus, bit 3
74 TIME MARK O One pulse per second output
75 RTCINT
I Real time clock interrupt input
76 MARKFB1
I Timemark line driver feedback
77 MARKFB2
I Timemark line driver feedback
78 D4
I/O Data Bus, bit 4
79 D5
I/O Data Bus, bit 5
80 VDD
81 VSS
82 D6
1 Positive supply
2 Ground
I/O Data Bus, bit 6
83 D7
I/O Data Bus, bit 7
84 WPROG
I Bus timing mode - see note 2
85 NANDA
I Test Structure - see note 3
86 NANDB
I Test Structure - see note 3
87 TDO
O Boundary Scan output
88 TCK
I Boundary Scan clock
89 TRST
I Boundary Scan reset
90 NANDOP
O Test Structure - see note 3
91 TMS
I Boundary Scan control
92 TDI
I Boundary Scan input
93 MARKFB3
I Timemark line driver feedback
94 TDO7
O Serial Test Data Output 7
95 DISCOP
O On/Off control for LNA by GP1010
96 TDO6
O Serial Test Data Output 6
97 TDO5
O Serial Test Data Output 5
98 D8
I/O Data Bus, bit 8
99 D9
I/O Data Bus, bit 9
100 VSS
101 VDD
102 D10
2 Ground
1 Positive supply
I/O Data Bus, bit 10
103 D11
I/O Data Bus, bit 11
104 TDO4
O Serial Test Data Output 4
105 TDO3
O Serial Test Data Output 3
106 TDO2
O Serial Test Data Output 2
107 TDO1
O Serial Test Data Output 1
108 D12
I/O Data Bus, bit 12
109 D13
I/O Data Bus, bit 13
110 VDD
111 VSS
112 D14
1 Positive supply
2 Ground
I/O Data Bus, bit 14
113 D15
I/O Data Bus, bit 15
114 ALE
I Address Latch Enable,
bus control
115 A1
I Register Address, bit 1 (LSB)
116 A2
I Register Address, bit 2
117 A3
I Register Address, bit 3
118 A4
I Register Address, bit 4
119 A5
I Register Address, bit 5
120 A6
I Register Address, bit 6
NOTE 1. The functions of RW and WEN pins depend on whether the
GP1020 is in Motorola™ (MOT/INTEL = ‘1’) or Intel™ mode (MOT/INTEL
= ‘0’). In Motorola mode, WEN is an enable (active high) and RW is Read/
Write select (‘1’ = Read). In Intel mode RW is Read, active low, and WEN
is Write, also active low.
MOT/INTEL
1
1
0
0
Mode
Motorola
Motorola
Intel
Intel
WEN RW Function
1 0 Write
1 1 Read
1 0 Read
0 1 Write
NOTE 2. WPROG is used to modify the timing of bus operations; when it
is held HIGH the internal write signal is ORed with ALE to allow time for the
internal address lines to stabilise; when it is held LOW there is no delay
added to write. NOTE 3. NANDOP (pin 90) is the output of a spare gate with
inputs on NANDA (pin 85) and NANDB (pin 86).
3


3Pages


GP1020CGGPKR 電子部品, 半導体
GP1020
GP1020 BUS TIMING DIAGRAMS (continued)
WEN
tCVWRV
CS
tWLWH
tALVWRV
ALE
tAVWRV
A (8:1)
tAHOLD
ADDRESS VALID
tWRHCH
tCHALV
NEXT
R/W
D (15:0)
tRWVWENH
RW
tDSETUP
tDHOLD
DATA VALID
tWENLRWNV
Fig. 8 Motorola 68xxx mode WRITE. MOT/INTEL = 1,
WPROG = 0
SIGNAL PROCESSING OVERVIEW
Each channel of the GP1020 is fed with a 2-bit (or optionally
with a 1-bit) GPS digital IF at around 1·4MHz, from the input
multiplexer that connects one of ten signal sources to the
channel input. This signal is first brought to baseband using an
on-chip digital mixer driven by a programmable digital local
oscillator. It is then correlated with a C/A code internally gener-
ated by a programmable Gold code generator; the correlation
result is the sum of the comparisons of individual code chips over
a complete code period (an ‘epoch’ in GPS terminology). A large
positive or a large negative sum indicate good correlation but
with opposite modulation, where the size of ‘large’ will depend on
the current signal to noise ratio, while a small sum indicates poor
correlation and the need to adjust the loops or choose another
satellite.
These results form the ‘Accumulated Data’ and are made
available to the microprocessor to both control the tracking loops
and to give the broadcast satellite data, the ‘Navigation Mes-
sage’ when demodulated. Periodically, the code epoch count,
the code phase, and the carrier phase of all channels, are
sampled at the same instant to form the ‘Measurement Data’ and
are also made available to the processor.
DESCRIPTION OF BLOCKS (see Fig. 10)
CLOCK GENERATOR
The Clock Generator block generates the various clocks
required in the GP1020, which can be operated either as a
master or as a slave device. When it is operated as a master, the
Clock Generator block is driven by a 40MHz clock provided by
the accompanying front-end chip, the GP1010, and to drive the
slaves a 20MHz output SLAVE CLK is provided. When the
GP1020 is operated as a slave, it is driven only by this 20MHz
SLAVE CLK from the master device. In the master the
40MHz is divided in a counter to form seven clock phases to
control the data flow, but to get the same timing in the slaves twin
20MHz dividers use both high and low phases separately to give
the effect of 40MHz clocking.
When in master mode these seven phases are also used to
generate a sampling clock (SAMP CLK) output at 40MHz47 =
5·71MHz, which drives the data sampling clock input of the
GP1010. A 100/219kHz output is provided for use as a micro-
processor Programmable Interrupt Clock.
6
WEN
tCVWRV
CS
tALVWRV
ALE
A (8:1)
tAVWRV
tAHOLD
ADDRESS VALID
tWRHCH
tCHALV
NEXT
R/W
D (15:0)
tRWVWENH
RW
tRVDV
tRHDZ
DATA VALID
tWENLRWNV
Fig. 9 Motorola 68xxx mode READ. MOT/INTEL = 1,
WPROG = 0
TIMEBASE GENERATOR
The Time Base Generator produces, among other signals: a
505·05 µs free-running interrupt timebase INT OUT, a free-
running TIC OUT signal with a period which may be selected to
be either 100ms or 9·09ms (approximately), and a TIME MARK
signal with a 1 second period as an output which may be locked
to GPS time, UTC, or the receiver timebase by programming its
delay relative to the TIC, based on recent navigation solutions.
The TIC is mainly used to latch measurement data (epoch count,
code phase, code DCO phase and integrated carrier phase
( = DCO phase and cycle count)) of all six channels at the same
instant.
BITE INTERFACE
The Bite Interface block contains a register which allows
control over the built-in-test functions of the chip. In addition, this
register allows the processor to read the state of discrete input
pins, such as PLLLOCKIN connected to the status output of the
GP1010, and also to set the state of the BITE CNTL and the
DISCOP output pins. These can in turn, for example, be used to
drive the GP1010 BITE input pin and the LNA power on/off
select, respectively.
STATUS REGISTERS
The Status Registers block contains registers describing the
status of accumulated and measurement data provided by each
channel.
SIGNAL SELECTION BLOCK
The Signal Selection block contains a multiplexer which can
be programmed to direct any of the ten input sources to any of
the six tracking channels. This is needed in GLONASS where
frequency division multiplexing is used and separate local oscil-
lators are needed to receive each satellite, leading to separate
IF filter channels. An input selector may be desirable in GPS,
which uses code division multiplexing, to allow the use of multiple
antennae to overcome problems of incomplete sky visibility.
For SIGN inputs, LOW = 2, HIGH = 1; for MAG inputs,
LOW = 1, HIGH = 3.
TRACKING MODULE BLOCKS
The six Tracking Module blocks are all identical so that the
term CHx is used in the description to mean any of CH1, CH2,

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部品番号部品説明メーカ
GP1020CGGPKR

SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

Zarlink Semiconductor Inc
Zarlink Semiconductor Inc


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