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GM82C765 の電気的特性と機能

GM82C765のメーカーはHynix Semiconductorです、この部品の機能は「FLOPPY DISK SUBSYSTEM CONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 GM82C765
部品説明 FLOPPY DISK SUBSYSTEM CONTROLLER
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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GM82C765 Datasheet, GM82C765 PDF,ピン配置, 機能
GM82C765B
GM82C765B
FLOPPY DISK SUBSYSTEM CONTROLLER
General Description
The GM82C765B is a CMOS LSI device which interfaces a host
microprocessor to the floppy disk drive. It integrates the function of the
Formatter/Controller, Data Separator. Write Precompensation, Data rate
selection, Clock Generation, High Current Output Drivers, and TTL
compatible Schmitt Trigger Receivers. The GM82C765B consists of a
microprocessor interface, a microsequencer and a disk drive interface.
The host microprocessor interface of the GM82C765B supports a
12MHz, 286 microprocessor bus without the use of wait states. All inputs
within host microprocessor are Schmitt triggers, except for the data bus,
XTAL, and the host output sink 12mA.
Output drive capability is 20 LSTTL load, allowing direct
interconnection to bus structures without the use of buffers or transceivers.
On the disk drive interface, the GM82C765B includes data seperation that
has been designed to address high performance error rate on floppy disk
drives, and contains all the necessary logic to achieve classical 2nd order,
type2, phase locked loop performance. Write precompensation is included,
in addition to the usual formatting, encoding, decoding, step motor control,
and status sensing functions For PC/XT and PC/AT applications, the
device provides qualification of interrupt and DMA requests.
The disk drive interface of the GM82C765B connects directly to up to
four drives. All drive-related inputs are Schmitt triggers and the drive
outputs are open drain, and sink 48 mA.
The GM82C765B uses two clock inputs which provide the necessary
signals for internal timing. A 16MHz oscillator controls the data rate of
500, 250 and 125Kbits/sec, while a 9.6MHz oscillator controls the
300Kbit/sec data rate used in PC/AT designs.
The two XTAL oscillator circuits may be used for the 44-pin PLCC
package, while TTL clock inputs must be provided when using the 40-pin
DIP package.
In the PLCC version of the GM82C765B pins 17 and 40, which were
not utilized in DIP version of the GM82C765B, became DCHGEN (Disk
Change Enable) and DCHG (Disk Change) respectively. Both are active
LOW. DCHGEN is offered as an option for those designs that used the
original GM82C765B part where DCHG did not exist as direct into the
chip.
The GM82C765B has eight internal Registers. The 8 bit main status
register contains status information of the GM82C765B and may be
accessed any time. Another four status register under system control also
give various status and error information. The Control Register provides
support logic that latches the two LSBs used to select the desired data rate
that controls internal clock generation. The Operations Register replaces
the standard latched port used in floppy subsystem.
Features
IBM PC compatible format
(single and double density)
– Floppy disk control and
operations on chip
– In PC AT mode, provides required
signal qualification DMA channel
– BIOS compatible and dual speed
Spindle Drive support
Integrates Formatter/Controller/Data
Separation, Write Precompensation,
Data rate Selection, Clock
Generation, and drive interface
Drivers and Receivers into one chip
Multisector and Multitrack transfer
capability.
Direct Floppy Disk Drive interface
with no buffers needed
– 48mA sink output drivers
– Schmitt trigger Line Receivers
Enhanced Host Interface:
– Supports 12MHz, 286 u-processor
– Capable of driving 20 LSTTL
Load
Address mark detection circuitary
internal to Floppy Disk Controller
On chip Clock Generation
Two TTL Clock Inputs for 40-DIP
Two XTAL oscillator circuits for
44-Quad, PLCC
User programmable Track Stepping
Rate and Head load/unload time
Drivers up to four Floppy or micro
Floppy Disk Drives
Data transfer DMA or non-DMA
mode
Parallel seek operations on up to
four Drives
Internal power up reset circuitry
READ/WRITE access compatible
register with 8 or 12MHz 286
microprocessor with 0 wait states.
DMA timing corrected.
LOW POWER CMOS, +5V SUPPLY
1

1 Page





GM82C765 pdf, ピン配列
GM82C765B
PIN MENMO
DIP PLCC -MIC
SIGNAL
NAME
6 6 TC
TERMINAL
COUNT
7-14
7-14
DBO thru
DB7
DATA BUS 0
Thru
DATA BUS 7
15 15 DMA
DIRECT
MEMORY
ACCESS
16 16 IRQ
INTERRUPT
REQUEST
DISK
17 DCHGEN CHANGE
ENABLE
17 18 LDOR
LOAD
OPERATIONS
REGISTER
18 19 LDCR
LOAD
CINTROL
REGISTER
19 20 RST
RESET
20 21 RDD
22 XT2
23 XT2
READ DISK
DATA
XTAL2
XTAL2
21
CLK2
CLOCK2
(condinued on next page)
I/O FUNCTION
This signal indicates to GM82C765B that data transfer is
complete. If DMA operational mode is selected for
command execution, TC will be qualified by DACK , but
not in the programmed I/O execution. In PC AT or Special
I
ST
mode, qualification by DACK requires the Operations
mode, qualification by DACK requires the operations
resister signal DMAEN to be logically true. Note also that
in PC AT mode, TC will be qualified by DACK , whether in
DMA or non-DMA host operation. programmed I/O in PC
AT mode will cause an abnormal termination error at the
completion of a command.
I/O
BI
8-Bit bi-directional, tri-state, data bus.
D0 is the least significant bit (LSB).
D7 is the most significant bit (MSB)
DMA request for byte transfer of data.
O In Special or PC AT mode, this pin is tristated, enabled by
BI the DMAEN signal from the Operation Register. This pin is
driven in the Base mode.
Interrupt request indicating the completion of command
O
BI
execution or data transfer requests (in non DMA mode).
Normally driven in base mode. In special or PC AT mode,
this pin is tri-stated, enabled by the DMAEN signal from the
Operations Resister.
I
ST
This input must be at logic = 0 to enable DCHG input
status at pin 40 to be placed on DB7 during a RD = 0 of
LDCR = 0. Internal pull-up.
Address decode which enables the loading of the Operations
I Resister. Internally gated with WR creates the strobe
ST which latches the two LSBS from the data bus into the
Operation Resister.
Address decode which enables the loading of the Control
I Resister. Internally gated with WR creates the strobe
ST which latches the two LSRs from thedata bus into the
Control Resister.
I
ST
Reset controller, placing microsequencer in idle. Resets
device outputs. Puts in base mode, not PC AT or Special
mode.
I
ST
This is the raw serial bit stream from the disk drive. Each
falling edge of the pulses represents a flux transition of the
encoded data.
O XTAL oscillator drive output for 44 pin PLCC should be
N left floating if TTL inputs used at pin 23.
I XTAL oscillator input used for non-standard data rates. It
N may be driven with a TTL level signal
I
N
TTL level clock input used for non-standard data rates is
9.6MHz for 300 kbs, and can only be selected from the
Control Register. * XT2 (PIN23) of 44 pin-PLCC
3


3Pages


GM82C765 電子部品, 半導体
GM82C765B
2. Electrical Specifications.
2.1 Absolute Maximum Ratings
—OPERATING TEMPERATURE …………...…………. …0°…C…(3…2°F) to 70°C (158°F)
—STORAGE TEMPERATURE …………………-…55…°C…(…-67…°F…)…to…+125°C (257°F)
—VOLTAGE on any pin with respect to ground ……………. …–0….3 …V…to…Vcc +0.3V
—SUPPLY VOLTAGE with respect to ground ………………………. …7.…0V………………
2.2 DC ELECTRICAL CHARACTERISTICS
NOTE: Maximum limits indicate where permanent device damage occurs.
Continous operation at these limits is not intended and should be limited to those conditions specified in the DC operating Characteristics
DC Operating Caracteristics: TA = 0°C (32°F) to 70°C (158°F) ; VCC = 5V ± 10%
SYMBOL PARAMETER
VCC +5V DC POWER SUPPLY
VIL Input LOW Voltage-DATA BUS & XTOSC
VIH Input HIGH Voltage-DATA BUS & XTOSC
VILT
VIHT
Input LOW Threshold Voltage-Schmitt Trigger
Input HIGH Threshold Voltage-Schmitt Trigger
VOL
Output LOW-DBX, IRQ, DMA: lo=12.0mA
VOH
Output HIGH-DBX, IRQ, DMA: lo=-5.0mA
VOLHC Output LOW-HIGH CURRENT: lo=48mA
ILUL
Latch up CURRENT LOW
ILUH
Latch up CURRENT HIGH
ILLX
Leakage CURRENT LOW
ILHX
Leakage CURRENT HIGH
ICC Supply Current-100uA source Loads
ICCHL
Supply Current-5mA source Loads
PD Power Dissipation-ICC Max*
PDHL
Power Dissipation-ICCHL Max*
VPQR
Power Qualified Reset Threshold
NOTE:*:Includes open DRAIN High current drives at VOL=0.4V
MIN
4.5
2.0
0.8
MAX
5.5
0.8
UNITS
V
V
V
V
2.8
40.0
-40.0
2.8
2.0
0.4
0.4
20.0
-20.0
45.0
95.0
425.0
575.0
4.35
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
V
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
GM82C765

FLOPPY DISK SUBSYSTEM CONTROLLER

Hynix Semiconductor
Hynix Semiconductor
GM82C765B

FLOPPY DISK SUBSYSTEM CONTROLLER

Hynix Semiconductor
Hynix Semiconductor


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