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PDF GS9015ACTJ Data sheet ( Hoja de datos )
| Número de pieza | GS9015ACTJ | |
| Descripción | Serial Digital Reclocker | |
| Fabricantes | ETC | |
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GENLINX™ GS9015A
Serial Digital Reclocker
DATA SHEET
FEATURES
• reclocking of SMPTE 259M signals
• operational to 400 Mb/s
• adjustment free reclocker when used with the
GS9000B or GS9000S decoder and GS9010A
Automatic Tuning Sub-system
• 28 pin PLCC packaging
APPLICATIONS
• 4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces
ORDERING INFORMATION
PART NUMBER
GS9015ACPJ
GS9015ACTJ
PACKAGE
28 Pin PLCC
28 Pin PLCC Tape
TEMPERATURE
0O C to 70O C
0O C to 70O C
DEVICE DESCRIPTION
The GS9015A is a monolithic IC designed to receive SMPTE
259M serial digital video signals. This device performs the
function of data and clock recovery. It interfaces directly with
the GENLINX™ GS9000B or GS9000S Decoder.
While there are no plans to discontinue the GS9015A, Gennum
has developed a successor product with improved features
and performance called the GS9035. The GS9035 is
recommended for new designs.
The VCO centre frequencies are controlled by external resistors
which can be selected by applying a two bit binary code to the
Standards Select input pins. Alternatively, the GS9015A can
be used with the GS9010A to form an adjustment free reclocker
system.
The GS9015A is packaged in a 28 pin PLCC operating from
a single +5 or -5 volt supply.
SPECIAL NOTE: R and R are functional over a
VCO1
VCO2
reduced temperature range of TA=0°C to 50°C. RVCO0
and RVCO3 are functional over the full temperature range
of TA=0°C to 70°C. This limitation does not affect
operation with the GS9010A ATS.
DIGITAL 5,6
IN
DATA
LATCH
CARRIER 19
DETECT
CARRIER
DETECT
LOOP
FILTER 12
PLL
PHASE
COMPARATOR
÷2
CHARGE
PUMP
VCO
GS9015A
24
25
22
23
SERIAL DATA
SERIAL DATA
SERIAL CLOCK
SERIAL CLOCK
10
ƒ/2
STANDARD
SELECT
20 SS0
21 SS1
13 14 15 17
FUNCTIONAL BLOCK DIAGRAM
Revision Date: April 1998
Document No. 520 - 99 - 05
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946
Web Site: www.gennum.com E-mail: [email protected]
1 page  
GS9015A PIN DESCRIPTIONS cont.
PIN NO SYMBOL TYPE
DESCRIPTION
18
19
20,21
22,23
24,25
26
27
28
VCC2
CD
Output
Power Supply. Most positive power supply connection. (VCO, MUX, Standard Select).
Carrier Detect. Open collector output which goes HIGH when a signal is present at either the Serial
Data inputs or the Direct Digital inputs. This output is used in conjunction with the GS9000B or GS9000S
in the Automatic Standards Select Mode to disable the 2 bit standard select counter. This pin should
see a low AC impedance (e.g. 1nF to AC Gnd)
SS0, SS1 Inputs
Standard Select Inputs. TTL inputs to the 2:4 multiplexer used to select one of four VCO centre
frequency setting resistors (RVCO0 - RVCO3). When both SS0 and SS1 are LOW, RVCO0 is selected.
When SS0 is HIGH and SS1 is LOW, RVCO1 is selected. When SS0 is LOW and SS1 is HIGH, RVCO2
is selected and when both SS0 and SS1 are HIGH, RVCO3 is selected. These pins should see a
low AC impedance (e.g. 1nF to AC Gnd)
SCO/SCO Outputs
SDO/SDO Outputs
VCC3
VEE2
VEE1
Serial Clock Outputs (inverse and true). Pseudo-ECL differential outputs of the extracted serial clock.
These outputs require a 390 Ω pull-down resistors to VEE.
Serial Data Outputs (inverse and true). Pseudo-ECL differential outputs of the regenerated serial data.
These outputs require a 390 Ω pull-down resistors to VEE.
Power Supply. Most positive power supply connection. (ECL Outputs).
Power Supply. Most negative power supply connection. (Phase Detector, Carrier Detect)
Power Supply. Most negative power supply connection.
INPUT / OUTPUT CIRCUITS
VCC
+ 1.2V
-
2k 2k
1k 1k
DDI
Pin 5
DDI
Pin 6
380µA
+
- 1.6V
Fig. 3 Pins 1, 5 and 6
5
520 - 99 - 05
5 Page 
Temperature Compensation
Figure 15 shows the connections for the frequency setting
resistors for the various data rates. The compensation shown
for 360 Mb/s and 177 Mb/s with Divide by 2 ON, is useful to
a maximum ambient temperature of 50°C. If the Divide by 2
function is not enabled by the ƒ/2 ENABLE input, no
compensation is needed for the 143 Mb/s and 177 Mb/s data
rates. The resistor connections are shown in Figure 16. In both
cases , the 0.1µF capacitor that bypasses the potentiometer
should be star routed to VEE3.
5.6k 1.3k
1N914
5k
0.1µF
4.3k 1.3k
1N914
5k
0.1µF
VEE VEE
Divide by 2 is OFF
Divide by 2 is ON
270 Mb/s using RVCO0 or RVCO1 143 Mb/s using RVCO2 or RVCO3
1k 1k
1k 1k
0.1µF
0.1µF
1N914
1N914
VEE
Divide by 2 is OFF
VEE
Divide by 2 is ON
360 Mb/s using RVCO0 or RVCO1 177 Mb/s using RVCO2 or RVCO3
Fig. 15 Frequency Setting Resistor Values
& Temperature Compensation
Temperature Compensation Procedure
In order to correctly set the VCO frequency so that the PLL will
always re-acquire lock over the full temperature range, the
following procedure should be used. The circuit should be
powered on for at least one minute prior to starting this
procedure.
Monitor the loop filter voltage at the junction of the loop filter
resistor and 10 nF loop filter capacitor (LOOP FILTER TEST
POINT). Using the appropriate network shown above, the
VCO frequency is set by first tuning the potentiometer so that
the PLL loses lock at the low end (lowest loop filter voltage).
The loop filter voltage is then slowly increased by adjusting the
the potentiometer to determine the error free low limit of the
capture range. Error free operation is determined by using a
suitable CRC or EDH measurement method to obtain a stable
signal with no errors. Record the loop filter voltage at this point
as VCL. Now adjust the potentiometer so that the loop filter
voltage is 250 mV above VCL.
1k
5k
0.1µF
VEE
Divide by 2 is OFF
143Mb/s and 177 Mb/s using any RVCO pins
Fig. 16 Non - Temperature Compensated Resistor Values
for 143 Mb/s and 177 Mb/s
Loop Bandwidth
The loop bandwidth is dependant upon the internal PLL gain
constants along with the loop filter components connected to
pin 12. In addition, the impedance seen by the RVCO pin also
influences the loop characteristics such that as the imped-
ance drops, the loop gain increases.
Applications Circuit
Figure 17 shows an application of the GS9015A in an
adjustment free, multi-standard serial to parallel convertor.
This circuit uses the GS9010A Automatic Tuning Sub-
system IC and a GS9000B or GS9000S Decoder IC.
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the
incoming data stream is 4ƒsc NTSC,4ƒsc PAL or component
4:2:2.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Reclocker VCO frequency over a
set range until the system is correctly locked. An automatic
fine tuning (AFT) loop maintains the Reclocker VCOcontrol
voltage at it's centre point through continuous, long term
adjustments of the VCO centre frequency.
During normal operation, the GS9000B or GS9000S Decoder
provides continuous HSYNC pulses which disable the
ramp/oscillator of the GS9010A. This maintains the
correct Reclocker VCO frequency. When an interruption
to the incoming data stream is detected by the Reclocker,
the Carrier Detect goes LOW and opens the AFT loop in
order to maintain the correct VCO frequency for a period
of at least 2 seconds. This allows the Reclocker to rapidly
relock when the signal is re-established.
11 520 - 99 - 05
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