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GS9015ACPJ の電気的特性と機能

GS9015ACPJのメーカーはETCです、この部品の機能は「Serial Digital Reclocker」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS9015ACPJ
部品説明 Serial Digital Reclocker
メーカ ETC
ロゴ ETC ロゴ 




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GS9015ACPJ Datasheet, GS9015ACPJ PDF,ピン配置, 機能
GENLINXGS9015A
Serial Digital Reclocker
DATA SHEET
FEATURES
• reclocking of SMPTE 259M signals
• operational to 400 Mb/s
• adjustment free reclocker when used with the
GS9000B or GS9000S decoder and GS9010A
Automatic Tuning Sub-system
• 28 pin PLCC packaging
APPLICATIONS
• 4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces
ORDERING INFORMATION
PART NUMBER
GS9015ACPJ
GS9015ACTJ
PACKAGE
28 Pin PLCC
28 Pin PLCC Tape
TEMPERATURE
0O C to 70O C
0O C to 70O C
DEVICE DESCRIPTION
The GS9015A is a monolithic IC designed to receive SMPTE
259M serial digital video signals. This device performs the
function of data and clock recovery. It interfaces directly with
the GENLINXGS9000B or GS9000S Decoder.
While there are no plans to discontinue the GS9015A, Gennum
has developed a successor product with improved features
and performance called the GS9035. The GS9035 is
recommended for new designs.
The VCO centre frequencies are controlled by external resistors
which can be selected by applying a two bit binary code to the
Standards Select input pins. Alternatively, the GS9015A can
be used with the GS9010A to form an adjustment free reclocker
system.
The GS9015A is packaged in a 28 pin PLCC operating from
a single +5 or -5 volt supply.
SPECIAL NOTE: R and R are functional over a
VCO1
VCO2
reduced temperature range of TA=0°C to 50°C. RVCO0
and RVCO3 are functional over the full temperature range
of TA=0°C to 70°C. This limitation does not affect
operation with the GS9010A ATS.
DIGITAL 5,6
IN
DATA
LATCH
CARRIER 19
DETECT
CARRIER
DETECT
LOOP
FILTER 12
PLL
PHASE
COMPARATOR
÷2
CHARGE
PUMP
VCO
GS9015A
24
25
22
23
SERIAL DATA
SERIAL DATA
SERIAL CLOCK
SERIAL CLOCK
10
ƒ/2
STANDARD
SELECT
20 SS0
21 SS1
13 14 15 17
FUNCTIONAL BLOCK DIAGRAM
Revision Date: April 1998
Document No. 520 - 99 - 05
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946
Web Site: www.gennum.com E-mail: [email protected]

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GS9015ACPJ pdf, ピン配列
SERIAL
DATA OUT
(SD0)
SERIAL
CLOCK OUT
(SCK)
tD
50%
tD
50%
Fig.1 Waveforms
GS9015A Reclocking Receiver - Detailed Device Description
The GS9015A Reclocking Receiver is a bipolar integrated
circuit containing circuitry necessary to re-clock and regenerate
the NRZI serial data stream.
Packaged in a 28 pin PLCC, the receiver operates from a
single five volt supply at data rates to 400 Mb/s. Typical power
consumption is 330 mW. Typical output jitter is ± 100 ps at
270 Mb/s.
Serial Digital signals are applied to digital inputs DDI and DDI
(pins 5,6).
Phase Locked Loop
The phase comparator itself compares the position of
transitions in the incoming signal with the phase of the local
oscillator (VCO). The error-correcting output signals are fed
to the charge pump in the form of short pulses. The charge
pump converts these pulses into a “charge packet” which is
accurately proportional to the system phase error.
The charge packet is then integrated by the second-order
loop filter to produce a control voltage for the VCO.
During periods when there are no transitions in the signal, the
loop filter voltage is required to hold precisely at its last value
so that the VCO does not drift significantly between corrections.
Commutating diodes in the charge pump keep the output
leakage current extremely low, minimizing VCO frequency
drift.
The VCO is implemented using a current-controlled
multivibrator, designed to deliver good stability, low phase
noise and wide operating frequency capability. The frequency
range is design-limited to ± 10% about the oscillator centre
frequency.
VCO Centre Frequency Selection
The centre frequency of the VCO is set by one of four external
current reference resistors (RVCO0-RVCO3) connected to
pins 13,14,15 or 17. These are selected by two logic inputs
SS0 and SS1 (pins 20, 21) through a 2:4 decoder according
to the following truth table.
SS1 SS0
00
01
10
11
Resistor Selected
RVCO0 (13)
RVCO1 (14)
RVCO2 (15)
RVCO3 (17)
As an alternative, the GS9010A Automatic Tuning Sub-system
and the GS9000B or GS9000S Decoder may be used in
conjunction with the GS9015A to obtain adjustment free and
automatic standard select operation (see Figure17).
With the VCO operating at twice the clock frequency, a clock
phase which is centred on the eye of the locked signal is used
to latch the incoming data, thus maximising immunity to
jitter-induced errors. The alternate phase is used to latch the
output re-clocked data SDO and SDO (pins 25, 24). The true
and inverse clock signals themselves are available from the
SCO and SCO pins 23 and 22.
3 520 - 99 - 05


3Pages


GS9015ACPJ 電子部品, 半導体
INPUT / OUTPUT CIRCUITS cont.
IVCO
(1.9 - 2.4V)
Pin 13 RVCO 0
Pin 14 RVCO 1
Pin 15 RVCO 2
Pin 17 RVCO 3
400
400
400
400
Fig. 4 Pins 13, 14, 15 and 17
VCC
200 200
VCC3
LOOP FILTER
(1.8 - 2.7V)
10k 10k
VCC
VCC
3k
SDO or SCO
Pin 25, 24
SDO or SCO
Pin 23, 22
800
Fig. 5 Pins 25, 24, 23 and 22
520 - 99 - 05
6

6 Page



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部品番号部品説明メーカ
GS9015ACPJ

Serial Digital Reclocker

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