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GS9010ACKC の電気的特性と機能

GS9010ACKCのメーカーはETCです、この部品の機能は「Serial Digital Automatic Tuning Subsystem」です。


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部品番号 GS9010ACKC
部品説明 Serial Digital Automatic Tuning Subsystem
メーカ ETC
ロゴ ETC ロゴ 




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GS9010ACKC Datasheet, GS9010ACKC PDF,ピン配置, 機能
GENLINXGS9010A Serial Digital
Automatic Tuning Subsystem
FEATURES
when used with the GS9005A or GS9015A and the
GS9000B or GS9000S, the GS9010A:
- constitutes an automatic 'tweakless' Serial
Digital receiving system
- eliminates the need for trim pots and external
temperature compensation for bit rates to 370 Mb/s
- automatically determines whether data is 4ƒsc
or 4:2:2, and whether the 4ƒsc data is NTSC or
PAL
- acquires lock from a 'no signal' condition in typically
50 ms
- holds lock during data interruptions for typically 2s
- relocks from synchronous switching in less than
10 µs
16 pin SOIC packaging
operates from a single +5 or -5 volt supply
typically consumes only 40 mW
immunity to spurious HSYNC inputs
defines minimum GS9005A VCO frequency after
extended absence of input signal
matches GS9005A capture range
APPLICATIONS
• 4ƒsc, 4:2:2 & 360 Mb/s serial digital interfaces
ORDERING INFORMATION
Part Number
Package Type
Temperature Range
GS9010ACKC 16 Pin Wide SOIC
0° to 70° C
GS9010ACTC 16 Pin Wide SOIC Tape
0° to 70° C
DEVICE DESCRIPTION
DATA SHEET
The GENLINXGS9010A is a monolithic integrated
circuit designed to be an Automatic Tuning Subsystem
(ATS) when used with the GS9005A Receiver or the
GS9015A Reclocker and the GS9000B or GS9000S Decoder.
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the
incoming data stream is 4ƒsc NTSC, 4ƒsc PAL or component
4:2:2.
The GS9010A is an enhanced version of the GS9010. Pin
compatible with the GS9010, the GS9010A offers improved
noise immunity to spurious HSYNC signals.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver/Reclocker VCO frequency
over a set range until the system is correctly locked. Once
locked, an automatic fine tuning (AFT) loop maintains the
VCO control voltage at its optimum centre point over
variations in temperature. During normal operation, the
GS9000B or GS9000S Decoder provides continuous HSYNC
pulses which disable the ramp/oscillator of the GS9010A.
This maintains the correct Receiver/Reclocker VCO
frequency. When an interruption to the incoming data
stream is detected by the Receiver/Reclocker, the Carrier
Detect goes LOW and opens the AFT loop in order to
maintain the correct VCO frequency for a period of typically
2 seconds. If the signal is re-established within this 2
seconds, the Receiver/Reclocker will rapidly relock. For
periods longer than typically 2 seconds, the VCO slowly
drifts towards a minimum frequency. Typically after 2
minutes, the serial clock output of the PLL settles to
approximately 85 MHz when ƒ/2 is high or 170 MHz
when ƒ/2 is low. The GS9010A is packaged in a 16 pin
wide SOIC, operates from a single +5 or -5 volt supply
and typically consumes 40 mW of power.
PAL/NTSC
FREQUENCY
COMPENSATION
1
4
LOOP FILTER
(from GS9005A)
5
CARRIER DETECT
(from GS9005A) 14
18k
11
OSCILLATOR
ƒ/2 6
(to GS9005A)
DELAY 10
÷4
VREF
20k
+
-
+
-
OSCILLATOR
COMPOSITE /
COMPONENT
DETECTOR
16 STANDARDS
THRESHOLD ADJUST
2 OUT
(to GS9005A)
3
IN-
13 HSYNC
( (from GS9000B
o orGS9000S)
25k8
SWF
(from GS9000B
or GS9000S)
9
FV CAP
Revision Date: August 1997
FUNCTIONAL BLOCK DIAGRAM
Document No. 521 - 01 - 05
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan Corporation: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839

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GS9010ACKC pdf, ピン配列
SYSTEM DESCRIPTION
The GS9005A Receiver or GS9015A Reclocker along with the
GS9000B or GS9000S Decoder form a serial to parallel decoding
system for Serial Digital Video signals. Use of the GS9010A
eliminates the need to manually tune the VCO and externally
temperature compensate for all data rates. Figure 1 shows a
simplified block diagram of the Automatic Tuning Sub-System
and Figure 2 shows the relevant waveforms.
The active high CARRIER DETECT output of the Receiver/
Reclocker indicates the presence of serial data. If the CARRIER
DETECT input to the GS9010A (pin 14) is HIGH (see Fig 2. [A])
and a Timing Reference Signal (TRS) is not being detected by
the GS9000B or GS9000S Decoder, an oscillator in the GS9010A
produces a s a w t o o t h r a m p s i g n a l a t t h e O U T p i n
( p i n 2 ) ( s e e Figure 2. [C]). This output is connected to the
Receiver/Reclocker RVCO pin via a resistor which converts this
voltage ramp into a current ramp. The frequency of the VCO is
changed by varying the current drawn from the RVCO pin such
that a lower sweep voltage at pin 2 of the GS9010A causes a
higher VCO frequency.
As the frequency sweeps, the PLL will lock to the incoming data
stream and the GS9000B or GS9000S decoder will detect TRS.
The TRS detect function is provided by the HSYNC output of the
GS9000B or GS9000S. In this case, HSYNC is a digital signal
which changes state whenever TRS is detected. This signal is
connected to the HSYNC input (pin 13) of the GS9010A (see
Figure 2 [B]). This signal will be at a rate equal to one half the
horizontal scan rate for composite video and equal to the
horizontal scan rate for component video since both EAV and
SAV produce an HSYNC state change. The presence of
detected TRS will shut off the GS9010A oscillator and disable
the sweep. Even though the oscillator is off, the Automatic Fine
Tuning (AFT) function provided by the buffer amplifier in the
GS9010A remains in the control loop in order to centre the
GS9005A or GS9015A loop filter voltage to VREF (approximately
2.3V).
The VCO within the GS9005A or GS9015A has a dual modulus
divider feature which optimises jitter performance for the lower
data rates. This feature is enabled by a logic HIGH on the ƒ/2
pin. The MODULUS CONTROL output (pin 6) (see Figure 2.
[D]) of the GS9010A controls this ƒ/2 function to set the VCO
frequency to twice the normal rate. Under normal operation the
VCO within the GS9005A or GS9015A, operates at twice the
output clock frequency, which means that for 360 Mb/s data the
VCO is operating at 720 MHz (2 x 360 MHz). For 177 Mb/s (PAL
- 4fsc), with the ƒ/2 function enabled, the VCO operates at 708
MHz (2 x 2 x 177 MHz). In the case of component and
composite NTSC, the VCO operates at 540 MHz (2 x 270 MHz)
and 572 MHz (2 x 2 x 143 MHz) respectively. This means that
the VCO is tuned to the same frequency range for 4:2:2 and the
respective 4ƒsc signals.
The MODULUS CONTROL itself is derived by dividing the
GS9010A oscillator by four. It is possible that the PLL could lock
with the MODULUS CONTROL in the wrong state (ƒ/2 OFF) for
component data rates.
In order to avoid this, another circuit ensures that the MODULUS
CONTROL is set HIGH (ƒ/2 ENABLED) for composite data
rates and LOW (ƒ/2 OFF) for component data rates. This is
accomplished through a Frequency Detector (Frequency to
Voltage Convertor, FVC) which measures the frequency of
HSYNC and compares it to a reference. If the frequency of
HSYNC corresponds to composite video, the comparator
output is high and the ÷ 4 (MODULUS CONTROL) is set HIGH.
Conversely, when the frequency of HSYNC corresponds to
component video, the MODULUS CONTROL is set LOW.
If the FVC measurement results in any change to the MODULUS
CONTROL, the PLL will immediately lose lock, the TRS will not
be detected and the oscillator will begin to sweep the VCO
frequency. Now the PLL will reacquire lock with the MODULUS
CONTROL in the correct state before the ÷ 4 output changes
state.
In a noisy environment or at power-on, erratic TRS will cause
the GS9000B or GS9000S to output an artificially low HSYNC
frequency. This condition often subsides after input data
stabilizes or in the case of power-up, once the supplies have
settled. The GS9010A employs a technique to provide noise
immunity within the COMPOSITE/COMPONENT DETECTOR
(CCD) to protect against erroneous modulus settings. This
technique is explained in the following paragraph.
A delay is required for the FVC calculation within the CCD
before the ÷ 4 is set/reset. In the GS9010A, the trigger
threshold for this delay is controlled by the ƒ/2 and FVCAP
output voltage. Because this threshold is modulated, the
incoming HSYNC frequency must be compatible with the
current ƒ/2 state before the delay is triggered. This threshold
control prevents artificially low HSYNC frequencies from
triggering the set/reset of the ÷ 4 thus preventing the wrong
MODULUS CONTROL.
If the serial digital signal is interrupted, CARRIER DETECT
(pin 14) goes LOW and turns the internal oscillator off. The
buffer from the LOOP FILTER input (pin 5) to the 20 k
integrator resistor is disabled and its output becomes high
impedance, neither sinking nor sourcing current. In this state,
the output voltage from the GS9010A will remain constant for
a time period of typically 2 seconds. The VCO in the Receiver/
Reclocker will remain tuned to the correct frequency so that
the PLL will relock quickly without frequency sweeping when
the serial data returns. For longer periods of data interruption,
the external integration capacitor between the OUT and IN
pins will slowly discharge and the VCO will drift lower in
frequency. The serial clock output frequency of the PLL will
settle to approximately 170 MHz when ƒ/2 is high and 85 MHz
when ƒ/2 is low. A limit has been set on the maximum OUT
voltage to prevent Receiver/Reclocker VCOshutdown allowing
faster relock time once data is reapplied.
3 521 - 01 - 05


3Pages


GS9010ACKC 電子部品, 半導体
VCC
+5V
+
10µ
GND
INPUT 75
75
DVCC
+5V
+
10µ
DGND
10µ
+
0.1µ
VCC
0.1µ
ECL
DATA
INPUT
VCC
5
DDI
6
0.1µ
DDI
7 VCC2
47p 8 SDI
9 SDI
10 ƒ/2
47p 11 VEE3
SSI
0.1µ
VCC
0.1µ
4 3 2 1 28 27 26
GS9005A
25
SDO
24
SDO
SCO 23
SCO 22
SS1 21 VCC
SS0 20
CD 19
5.6p
12 13 14 15 16 17 18 VCC
VCC
22n(1) 113
(2)
10n
910
0.1µF
1.2k
SWF
390
390
100
100
100
100
390
390
VCC
100 3.3k
100
DGND
100
DGND
DGND
4 3 2 1 28 27 26
5
SDI
6
SDI
7
SCI
8
SCI
9 SS1
10 SS0
11 SST
(4)
GS9000B
or GS9000S
25
PD7
24
PD6
23
PD5
22
PD4
PD3 21
PD2 20
PD1 19
DVCC
DVCC 12 13 14 15 16 17 18
0.1µ
0.1µ
100 100
DGND
DGND
DVCC
100
100
100
100
100
100
100
INPUT SELECTION
SYNC WARNING FLAG
HSYNC OUTPUT
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
STAR
ROUTED
0.1µ
6.8µ +
(2)
6.8µ +
VCC
0.1µ
1.2k
120
GS9010A
1
2
3
4
3.3n 5
6
7
8
P/N
OUT
IN-
COMP
LF
ƒ/2
VCC
SWF
STDT
VCC
CD
HSYNC
GND
OSC
DLY
FVCAP
16
15
14
13
12
11
10
9
SWF
(3)
50k
VCC
0.1µ
82n
VCC
180n
68k 22n
DGND
VCC
100k
(2)
0.68µ
STANDARD TRUTH TABLE
ƒ/2 P/N
00
01
10
11
STANDARD
4:2:2 - 270
4:2:2 - 360
4ƒsc - NTSC
4ƒsc - PAL
All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated.
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8 µF capacitors (connected across pins 2 and 3 of the GS9010A)
may be replaced with a 1.0 µF non-polarized capacitor provided that:
(a) the 0.68 µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33 µF capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10 nF.
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
(4) The GS9000B will operate to a maximum frequency of 370 Mbps.
The GS9000S will operate to a maximum frequency of 300 Mbps.
Fig. 3 Typical Application Circuit
DOCUMENT
IDENTIFICATION
PRODUCT PROPOSAL
This data has been compiled for market investigation purposes
only, and does not constitute an offer for sale.
REVISION NOTES
Figures 1 and 3 updated
ADVANCE INFORMATION NOTE
This product is in development phase and specifications are
subject to change without notice. Gennum reserves the right to
remove the product at any time. Listing the product does not
constitute an offer for sale.
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
PRELIMINARY
The product is in a preproduction phase and specifications are
subject to change without notice.
DATA SHEET
The product is in production. Gennum reserves the right to
make changes at any time to improve reliability, function or
design, in order to provide the best product possible.
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright January 1994 Gennum Corporation. All rights reserved. Printed in Canada.
521 - 01 - 05
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部品番号部品説明メーカ
GS9010ACKC

Serial Digital Automatic Tuning Subsystem

ETC
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