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GS84032AT-166I の電気的特性と機能

GS84032AT-166IのメーカーはETCです、この部品の機能は「256K x 18/ 128K x 32/ 128K x 36 4Mb Sync Burst SRAMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS84032AT-166I
部品説明 256K x 18/ 128K x 32/ 128K x 36 4Mb Sync Burst SRAMs
メーカ ETC
ロゴ ETC ロゴ 




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GS84032AT-166I Datasheet, GS84032AT-166I PDF,ピン配置, 機能
TQFP, BGA
Commercial Temp
Industrial Temp
Preliminary
GS84018/32/36AT/B-180/166/150/100
256K x 18, 128K x 32, 128K x 36 180 MHz–100 MHz
4Mb Sync Burst SRAMs
3.3 V VDD
3.3 V and 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP or 119-Bump BGA package
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
tKQ
IDD
tKQ
tCycle
IDD
–180
5.5 ns
3.0 ns
185 mA
8 ns
9.1 ns
115 mA
–166
6.0 ns
3.5 ns
170 mA
8.5 ns
10 ns
105 mA
–150
6.6 ns
3.8 ns
155 mA
10 ns
12 ns
100 mA
–100
10 ns
4.5 ns
105 mA
12 ns
15 ns
80 mA
Functional Description
Applications
The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS84018/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS84018/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to de-couple output noise
from the internal circuit.
Rev: 1.12 7/2002
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

1 Page





GS84032AT-166I pdf, ピン配列
GS84032A 100-Pin TQFP Pinout
Preliminary
GS84018/32/36AT/B-180/166/150/100
NC
DQC8
DQC7
VDDQ
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 128K x 32
10
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
Rev: 1.12 7/2002
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.


3Pages


GS84032AT-166I 電子部品, 半導体
GS84018A Pad Out
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Preliminary
GS84018/32/36AT/B-180/166/150/100
119-Bump BGA—Top View
1234567
VDDQ
NC
A6
E2
A7 ADSP A8
A4 ADSC A15
A9 VDDQ
E3 NC
NC
A5
A3
VDD
A14
A16
NC
DQB1 NC VSS NC VSS DQA9 NC
NC
DQB2
VSS
E1
VSS
NC DQA8
VDDQ NC
VSS
G
VSS DQA7 VDDQ
NC DQB3 BB
ADV NC
NC DQA6
DQB4 NC VSS GW VSS DQA5 NC
VDDQ VDD NC VDD NC VDD VDDQ
NC
DQB5
VSS
CK
VSS
NC
DQA4
DQB6
NC
NC
NC
BA DQA3 NC
VDDQ DQB7
VSS
BW
VSS
NC VDDQ
DQB8 NC VSS
A1
VSS DQA2
NC
NC
DQB9
VSS
A0
VSS
NC DQA1
NC A2 LBO VDD FT A13 NC
NC A10 A11 NC A12 A17 ZZ
VDDQ NC NC NC NC NC VDDQ
Rev: 1.12 7/2002
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.

6 Page



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部品番号部品説明メーカ
GS84032AT-166

256K x 18/ 128K x 32/ 128K x 36 4Mb Sync Burst SRAMs

ETC
ETC
GS84032AT-166I

256K x 18/ 128K x 32/ 128K x 36 4Mb Sync Burst SRAMs

ETC
ETC


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