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PDF HCF4031B Data sheet ( Hoja de datos )
| Número de pieza | HCF4031B | |
| Descripción | 64-STAGE STATIC SHIFT REGISTER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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HCC/HCF4031B
64-STAGE STATIC SHIFT REGISTER
. FULLY STATIC OPERATION : DC to 16MHz
(TYP.) @ VDD – VSS = 15V
. STANDARD TTL DRIVE CAPABILITY ON Q
OUTPUT
. RECIRCULATION CAPABILITY
. THREE CASCADING MODES :
DIRECT CLOCKING FOR HIGH-SPEED
OPERATION
DELAYED CLOCKING FOR REDUCED CLOCK
DRIVE REQUIREMENTS
ADDITIONAL 1/2 STAGE FOR SLOW CLOCKS
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
. 5V, 10V, AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100nA at 18V AND 25°C
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD NO. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4031BF HCF4031BEY
HCF4031BC1
PIN CONNECTIONS
DESCRIPTION
The HCC4031B (extended temperature range) and
HCF4031B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package.
The HCC/HCF4031B is a static shift register that
contains 64 D-type, master-slave flip-flop stages
and one stage which is a D-type master flip-flop only
(referred to as a 1/2 stage). The logic level present
at the DATA input is transferred into the first stage
and shifted one stage at each positive-going clock
transition. Maximum clock frequencies up to 16
Megahertz (typical) can be obtained. Because fully
static operation is allowed, information can be per-
manently stored with the clock line in either the low
or high state. The HCC/HCF4031B has a MODE
CONTROL input that, when in the high state, allows
operation in the recirculating mode. The MODE
CONTROL input can also be used to select between
two separate data sources. Register packages can
be cascaded and the clock lines driven directly for
high-speed operation. Alternatively, a delayed clock
output (CLD) is provided that enables cascading reg-
June 1989
1/12
1 page  
HCC/HCF4031B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200kΩ,
typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall times = 20ns)
Symbol
Parameter
tPHL ,
Propagation Delay Time :
t PL H, t PL H Clock to Q,
Clock to Q
Test Conditions
V al ue
V D D (V) Min. Typ. Max.
5 250 500
10 110 220
15 90 180
Unit
ns
tPHL ,
Propagation Delay Time :
t PL H, t PHL Clock to Q’
Clock to Q
5 190 380
10
80 160
ns
15 65 130
Clock to CLD
5 100 200
10
50 100
ns
t THL ’, tT L H Transition Time :
(any output, except QtTHL)
15 40 80
5 100 200
10
50 100
ns
tT HL
Q,
15 40 80
5 50 100
10
25 50
ns
15 20 40
t s e t u p Data Setup Time
5 30 60
10
15 30
ns
15 10 20
t h o ld Data Hold Time
5 30 60
10
15 30
ns
15 10 20
tW Clock Pulse Width
fmax Maximum Clock Input
Frequency**
tr, tf Clock Input Rise or Fall Time*
5 120 240
10
50 100
ns
15 40 80
5 24
10 5 10
MHz
15 6 12
5 1000
10 1000 µs
15 200
* If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of
the propagation delay at 50pF and the transmition time of the output driving stage.
* * Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode :
fmax =
(n-1)
CLD
prop.
delay
1
+
Q
prop.
delay
+
set-up
ti mewhere
n
=
nimber
of
packages
b) Not Usng Delaye Clock :
fmax =
1
propagation delay + set-up time
5/12
5 Page 
DIM.
A
B
D
d1
d2
E
e
e3
F
G
M
M1
MIN.
9.78
8.89
4.2
7.37
HCC/HCF4031B
PLCC20 MECHANICAL DATA
mm
TYP.
2.54
0.56
1.27
5.08
0.38
1.27
1.14
MAX.
10.03
9.04
4.57
MIN.
0.385
0.350
0.165
8.38 0.290
0.101
inch
TYP.
0.100
0.022
0.050
0.200
0.015
0.050
0.045
MAX.
0.395
0.356
0.180
0.330
0.004
P027A
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HCF4031B.PDF ] | |
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