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PDF VDIP1 Data sheet ( Hoja de datos )
| Número de pieza | VDIP1 | |
| Descripción | Vinculum VNC1L Module | |
| Fabricantes | FTDI | |
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Future Technology Devices International Ltd.
VDIP1
Vinculum VNC1L Module
Datasheet
Document Reference No.: FT_000016
Version 1.01
Issue Date: 2010-05-31
Future Technology Devices International Ltd (FTDI)
Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow, G41 1HH, United Kingdom
Tel.: +44 (0) 141 429 2777 Fax: + 44 (0) 141 429 2758
E-Mail (Support): [email protected]
Web: http://www.vinculum.com
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are
supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in
which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,
Glasgow, G41 1HH, United Kingdom. Scotland Registered Number: SC136640
Copyright © 2010 Future Technology Devices International Limited
1 page  
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3 Pin Out and Signal Description
3.1 Module Pin Out
Document Reference No.: FT_000016
VDIP1 Vinculum VNC1L Module Datasheet Version 1.01
Clearance No.: FTDI# 131
Figure 3.1 - VDIP1 Module Pin Out (Top View)
Copyright © 2010 Future Technology Devices International Limited
4
5 Page 
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3.6.2 SPI Slave Data Write Cycle
Document Reference No.: FT_000016
VDIP1 Vinculum VNC1L Module Datasheet Version 1.01
Clearance No.: FTDI# 131
When in SPI mode, the timing of a write operation is shown in
Figure 3.4 – SPI Slave Data Write Cycle.
From Start - SPI CS must be held high for the entire write cycle, and must be taken low for at least
one clock period after t he write is co mpletedThe. first bit on SPI Data In is the R/W bit - inputting
a ‘0’ here a llows data to be written to the chip. The next bit is the address bit, ADD, which is used
to indicate whether the data register (‘0’) or the status register (‘1’) is written to. During the SPI
write cycle a byte of data can be input to SPI Data In on the next clock cycle after t he address bit,
MSBAfterfirst.t he data has been clocked in to the chip, t he status of SPI Data Out should be
checked to see if the data read was accepted. A ‘0’ level on SPI Data Out means that the data
write was accepted. A ‘1’ indicates that the internal buffer is full, and the write should be repeated.
Remember that CS must be held low for at least one clock period before being taken high again to
continue with the next read or write cycle.
Copyright © 2010 Future Technology Devices International Limited
10
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet VDIP1.PDF ] | |
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