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HCPL-0870 の電気的特性と機能

HCPL-0870のメーカーはAgilent(Hewlett-Packard)です、この部品の機能は「Isolated 15-bit A/D Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCPL-0870
部品説明 Isolated 15-bit A/D Converter
メーカ Agilent(Hewlett-Packard)
ロゴ Agilent(Hewlett-Packard) ロゴ 




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HCPL-0870 Datasheet, HCPL-0870 PDF,ピン配置, 機能
H
Isolated 15-bit A/D Converter
Technical Data
HCPL-7860
HCPL-0870, -7870
Features
• 12-bit Linearity
• 700 ns Conversion Time
(Pre-Trigger Mode 2)
• 5 Conversion Modes for
Resolution/Speed Trade-Off;
12-bit Effective Resolution
with 18 µs Signal Delay
(14-bit with 94 µs)
• Fast 3 µs Over-Range
Detection
• Serial I/O (SPI®, QSPI® and
Microwire® Compatible)
± 200 mV Input Range with
Single 5 V Supply
• 1% Internal Reference
Voltage Matching
• Offset Calibration
• -40°C to +85°C Operating
Temperature Range
• 15 kV/µs Isolation Transient
Immunity
• Regulatory Approvals; UL,
CSA, VDE
DIGITAL CURRENT SENSOR
+ ISOLATION +
BOUNDARY
INPUT
CURRENT
OUTPUT
DATA
ISOLATED
MODULATOR
DIGITAL
INTERFACE IC
Hewlett-Packard’s Isolated A/D Converter delivers the reliability, small size, superior
isolation and over-temperature performance motor drive designers need to accurately
measure current at half the price of traditional solutions.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Inc.
1-260
5965-5255E

1 Page





HCPL-0870 pdf, ピン配列
isolated modulator without
additional hardware. Because the
two inputs are multiplexed, only
one conversion at a time can be
made and not all features are
available for the second channel.
The available features for both
channels are shown in the table
at right.
HCPL-x870 Digital Interface IC
Feature
Conversion Mode
Offset Calibration
Pre-Trigger Mode
Over-Range Detection
Adjustable Threshold Detection
Channel #1





Channel #2


Functional Diagrams
ISOLATION
BOUNDARY
VDD1 1
8 VDD2
VIN+ 2
VIN– 3
SIGMA-
DELTA
MOD./
ENCODE
7 MCLK
DECODE
6 MDAT
GND1 4
SHIELD
5 GND2
HCPL-7860 Isolated Modulator
CCLK 1
CLAT 2
CDAT 3
MCLK1 4
MDAT1 5
MCLK2 6
MDAT2 7
GND 8
CONFIG.
INTER-
FACE
CON-
VERSION
INTER-
FACE
CH1
16 VDD
15 CHAN
14 SCLK
13 SDAT
12 CS
THRES- 11 THR1
HOLD
CH2 DETECT 10 OVR1
&
RESET 9 RESET
HCPL-x870 Digital Interface IC
Pin Description, Isolated Modulator
Symbol
Description
VDD1
VIN+
Supply voltage input (4.5 V to 5.5 V)
Positive input (± 200 mV
recommended)
VIN– Negative input
(normally connected to GND1)
GND1 Input ground
Symbol
VDD2
MCLK
Description
Supply voltage input (4.5 V to 5.5 V)
Clock output (10 MHz typical)
MDAT Serial data output
GND2 Output ground
1-262


3Pages


HCPL-0870 電子部品, 半導体
Notes:
1. Resolution is defined as the total
number of output bits. The useable
accuracy of any A/D converter is a
function of its linearity and signal-to-
noise ratio, rather than how many
total bits it has.
2. Integral nonlinearity is defined as
one-half the peak-to-peak deviation
of the best-fit line through the
transfer curve for VIN+ = -200 mV to
+200 mV, expressed either as the
number of LSBs or as a percent of
measured input range (400 mV).
3. Differential nonlinearity is defined as
the deviation of the actual difference
from the ideal difference between
midpoints of successive output
codes, expressed in LSBs.
4. Data sheet value is the average
magnitude of the difference in offset
voltage from TA = 25°C to
TA = -40°C, expressed in microvolts
per °C.
5. All units within each HCPL-7860
standard packaging increment (either
50 per tube or 1000 per reel) have an
Absolute Reference Voltage tolerance
of ± 1%. An Absolute Reference
Voltage tolerance of ± 4% is
guaranteed between standard
packaging increments.
6. Beyond the full-scale input range the
output is either all zeroes or all ones.
7. The effective number of bits (or
effective resolution) is defined by the
equation ENOB = (SNR-1.76)/6.02
and represents the resolution of an
ideal, quantization-noise limited A/D
converter with the same SNR.
8. Conversion time is defined as the
time from when the convert start
signal CS is brought low to when
SDAT goes high, indicating that
output data is ready to be clocked
out. This can be as small as a few
cycles of the isolated modulator clock
and is determined by the frequency of
the isolated modulator clock and the
selected Conversion and Pre-Trigger
modes. For determining the true
signal delay characteristics of the A/D
converter for closed-loop phase
margin calculations, the signal delay
specification should be used.
9. Signal delay is defined as the effec-
tive delay of the input signal through
the Isolated A/D converter. It can be
measured by applying a -200 mV to
± 200 mV step at the input of modu-
lator and adjusting the relative delay
of the convert start signal CS so that
the output of the converter is at mid-
scale. The signal delay is the elapsed
time from when the step signal is
applied at the input to when output
data is ready at the end of the conver-
sion cycle. The signal delay is the
most important specification for
determining the true signal delay
characteristics of the A/D converter
and should be used for determining
phase margins in closed-loop applica-
tions. The signal delay is determined
by the frequency of the modulator
clock and which Conversion Mode is
selected, and is independent of the
selected Pre-Trigger Mode and,
therefore, conversion time.
10. The minimum and maximum over-
range detection time is determined by
the frequency of the channel 1 iso-
lated modulator clock.
11. The minimum and maximum thresh-
old detection time is determined by
the user-defined configuration of the
adjustable threshold detection circuit
and the frequency of the channel 1
isolated modulator clock. See the
Applications Information section for
further detail. The specified times
apply for the default configuration.
12. The signal bandwidth is the frequency
at which the magnitude of the output
signal has decreased 3 dB below its
low-frequency value. The signal
bandwidth is determined by the fre-
quency of the modulator clock and
the selected Conversion Mode.
13. The isolation transient immunity (also
known as Common-Mode Rejection)
specifies the minimum rate-of-rise of
an isolation-mode signal applied
across the isolation boundary beyond
which the modulator clock or data
signals are corrupted.
75.0
74.5
74.0
VDD1 = 4.5 V
VDD1 = 5.0 V
VDD1 = 5.5 V
73.5
73.0
72.5
-40
-20 0 20 40 60
TEMPERATURE – °C
85
16
14 VDD1 = 4.5 V
VDD1 = 5.0 V
12 VDD1 = 5.5 V
10
8
6
4
2
0
-40 -20 0 20 40 60
TEMPERATURE – °C
85
0.08
0.07
0.06
0.05
VDD1 = 4.5 V
VDD1 = 5.0 V
VDD1 = 5.5 V
0.04
0.03
0.02
0.01
0
-40
-20 0 20 40 60
TEMPERATURE – °C
85
Figure 2. SNR vs. Temperature.
Figure 3. INL (Bits) vs. Temperature. Figure 4. INL (%) vs. Temperature.
1-265

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
HCPL-0870

Isolated 15-bit A/D Converter

Agilent(Hewlett-Packard)
Agilent(Hewlett-Packard)
HCPL-0872

Digital Interface IC

Agilent Technologies
Agilent Technologies


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