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VDD8608A8A の電気的特性と機能

VDD8608A8AのメーカーはA-Dataです、この部品の機能は「DOUBLE DATA RATE SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 VDD8608A8A
部品説明 DOUBLE DATA RATE SDRAM
メーカ A-Data
ロゴ A-Data ロゴ 




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VDD8608A8A Datasheet, VDD8608A8A PDF,ピン配置, 機能
A-Data
Revision History
Revision 1 ( Dec. 2001 )
1.Fister release.
Revision 2 ( Apr. 2002 )
1. Changed module current specification.
2. Add Performance range.
3. Changed AC Characteristics.
4. Changed typo size on module PCB in package dimensions.
ADD8616A8A
Rev 2 April, 2002
1

1 Page





VDD8608A8A pdf, ピン配列
A-Data
ADD8616A8A
Pin Description
PIN
CK, /CK
CKE
NAME
System Clock
Clock Enable
/CS Chip Select
A0~A12 Address
BS0~BS1 Banks Select
DQ0~DQ15 Data
/RAS Row Address Strobe
/CAS Column Address Strobe
/WE Write Enable
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
VREF Reference Voltage
NC No Connection
FUNCTION
Differential clock input.
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A9
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS
low
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
Power supply for output buffers.
Reference voltage for inputs for SSTL interface.
This pin is recommended to be left No Connection on the device.
Block Diagram
CK
CKE
Clock
Generator
Address
/CS
/RAS
/CAS
/WE
Mode
Register
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank3
Bank2
Bank1
Bank0
Amplifier
Column Decoder
Data Control Circuit
DQM
DQS
DQ0~DQn
Rev 2 April, 2002
3


3Pages


VDD8608A8A 電子部品, 半導体
A-Data
DC Characteristics II
ADD8616A8A
Parameter
Symbol
Test condition
Operating Current
Precharge standby
current in power
down mode
IDD1
IDD2P
Burst length=2, One bank active
Trc=tRC(min),IOUT=0mA
CKEVIL(max), tCK=min
Speed
-75BA/ -75B
110
20
Unit Note
mA 1
mA
Precharge standby
CKEVIH(min), /CSVIH(min),
current in Non power IDD2N tCK= tCK min input signals are
down mode
changed one time during 2clks.
40
mA
Active standby
current in power
down mode
IDD3P CKEVIL(max), tCK= tCK min
20
mA
Active standby
CKEVIH(min), /CSVIH(min),
current in Non power IDD3N tCK=min input signals are
down mode
changed one time during 2clks.
65
mA
Burst mode operating
IDD4R
current
tCKtCK(min),IOUT=0 mA
All banks active
155 mA 1
Auto refresh current IDD5
tRRCtRRC(min), All banks
active
190
mA 2
Self refresh current IDD6 CKE0.2V
3 mA
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 2 April, 2002
6

6 Page



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部品番号部品説明メーカ
VDD8608A8A

DOUBLE DATA RATE SDRAM

A-Data
A-Data


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