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PDF ADUC7036 Data sheet ( Hoja de datos )
| Número de pieza | ADUC7036 | |
| Descripción | Integrated Precision Battery Sensor | |
| Fabricantes | ANALOG DEVICES | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADUC7036 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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Integrated Precision Battery Sensor
for Automotive
ADuC7036
FEATURES
High precision ADCs
Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs
Programmable ADC throughput from 1 Hz to 8 kHz
On-chip ±5 ppm/°C voltage reference
Current channel
Fully differential, buffered input
Programmable gain from 1 to 512
ADC input range: −200 mV to +300 mV
Digital comparators with current accumulator feature
Voltage channel
Buffered, on-chip attenuator for 12 V battery inputs
Temperature channel
External and on-chip temperature sensor options
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
20.48 MHz PLL with programmable divider
PLL input source
On-chip precision oscillator
On-chip low power oscillator
External (32.768 kHz) watch crystal
JTAG port supports code download and debug
Memory
96 kB Flash/EE memory, 6 kB SRAM
10,000-cycle Flash/EE endurance, 20-year Flash/EE
retention
In-circuit download via JTAG and LIN
On-chip peripherals
SAEJ2602/LIN 2.0-compatible (slave) support via UART
with hardware synchronization
Flexible wake-up I/O pin, master/slave SPI serial I/O
9-pin GPIO port, 3× general-purpose timers
Wake-up and watchdog timers
Power supply monitor and on-chip power-on reset
Power
Operates directly from 12 V battery supply
Current consumption
Normal mode 10 mA at 10 MHz
Low power monitor mode
Package and temperature range
48-lead, 7 mm × 7 mm LFCSP
Fully specified for −40°C to +115°C operation
APPLICATIONS
Battery sensing/management for automotive systems
FUNCTIONAL BLOCK DIAGRAM
IIN+
IIN–
VBAT
VTEMP
VREF
GND_SW
PRECISION ANALOG ACQUISITION
BUF PGA
16-BIT
Σ-∆ ADC
RESULT
DIGITAL
ACCUMULATOR COMPARATOR
MUX BUF
16-BIT
Σ-∆ ADC
TEMPERATURE
SENSOR
PRECISION
REFERENCE
ADuC7036
2.6V LDO
PSM
POR
MEMORY
98kB FLASH
6kB RAM
ARM7TDMI
MCU
20MHz
PRECISION
OSC
LOW POWER
OSC
ON-CHIP PLL
3× TIMERS
WDT
WU TIMER
GPIO PORT
UART PORT
SPI PORT
LIN
RESET
XTAL1
XTAL2
WU
STI
LIN/BSD
Figure 1.
Rev. C
Information furnished by Analog D evices is believed to b e accurate and reliable. However, no
responsibliity isassumed byAnalogDevices for its use,nor for any infringementsofpatentsorother
rightsof third partiesthat mayresultfrom its use.Specifications subjectto change withoutnotice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksaretheproperty oftheir respective owners.
One T echnology Way, P .O. B ox 91 06, Nor wood, MA 020 62-9106, U. S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved.
http://www.Datasheet4U.com
1 page  
Parameter Test
Voltage Channel13
No Missing Codes1
Integral Nonlinearity1
Offset Error3, 5
Offset Error1, 3
Offset Error Drift
Total Gain Error1, 3, 7, 10, 14
Total Gain Error1, 3, 7, 10, 14
Gain Drift
Output Noise1, 12, 15
Temperature Channel
No Missing Codes1
Integral Nonlinearity1
Offset Error3, 4, 5, 16
Offset Error1, 3
Offset Error Drift
Total Gain Error1,3,14
Gain Drift
Output Noise1
ADC SPECIFICATIONS ANALOG INPUT
Current Channel
Absolute Input Voltage Range
Input Voltage Range17, 18
Input Leakage Current1
Input Offset Current1, 20
Voltage Channel
Absolute Input Voltage Range
Input Voltage Range
VBAT Input Current
Temperature Channel
Absolute Input Voltage Range
Input Voltage Range
VTEMP Input Current1
Conditions/Comments
Valid at all ADC update rates
Chop off, 1 LSB = 439.5 μV
Chop on
Chop off
Includes resistor mismatch
Temperature range = −25°C to +65°C
Includes resistor mismatch drift
4 Hz update rate, ADCFLT = 0xBF1D
10 Hz update rate, ADCFLT = 0x961F
1 kHz update rate, ADCFLT = 0x0007
1 kHz update rate, ADCFLT = 0x8101
1 kHz update rate, ADCFLT = 0x0101
8 kHz update rate, ADCFLT = 0x0000
Valid at all ADC update rates
Chop off, 1 LSB = 19.84 μV in unipolar mode
Chop on
Chop off
Using REG_AVDD as the reference
1 kHz update rate
Internal VREF = 1.2 V
Applies to both IIN+ and IIN−
Gain = 119
Gain = 219
Gain = 419
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 256
Gain = 512
VBAT = 18 V
VREF = (REG_AVDD and GND_SW)/2
Min
16
−10
−0.25
−0.15
16
−10
−5
−0.2
ADuC7036
Typ Max
±10
±1
0.3
0.03
±0.06
±0.03
3
60
60
180
240
270
1600
±60
+10
1
+0.25
+0.15
90
90
270
307
405
2400
±10
±3
+1
0.03
±0.06
3
7.5
±60
+10
+5
+0.2
11.25
Unit
Bits
ppm of FSR
LSB
LSB
LSB/°C
%
%
ppm/°C
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
Bits
ppm of FSR
LSB
LSB
LSB/°C
%
ppm/°C
μV rms
−200
−3
4
3
100
±1.2
±600
±300
±150
±75
±37.5
±18.75
±9.375
±4.68
±2.3
0.5
+300
+3
1.5
0 to 28.8
5.5
18
8
0 to
VREF
2.5
1300
100
mV
V
mV
mV
mV
mV
mV
mV
mV
mV
mV
nA
nA
V
V
μA
mV
V
nA
Rev. C | Page 5 of 132
5 Page 
ADuC7036
Table 3. SPI Master Mode—Phase Mode = 0
Parameter Description
tSL SCLK low pulse width1
tSH SCLK high pulse width1
tDAV Data output valid after SCLK edge2
tDOSU Data output setup before SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge2
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
0
3 × tUCLK
0.5 tSL
3.5
3.5
3.5
3.5
1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD.
2 tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
Max
(2 × tUCLK) + (2 × tHCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI
tSH tSL
tDOSU
tDAV
tDF
MSB
tDR
BITS[6:1]
tSR tSF
LSB
MISO
MSB IN
BITS[6:1]
LSB IN
tDSU tDHD
Figure 3. SPI Master Mode Timing—Phase Mode = 0
Rev. C | Page 11 of 132
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet ADUC7036.PDF ] | |
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