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PDF GD25Q128B Data sheet ( Hoja de datos )
| Número de pieza | GD25Q128B | |
| Descripción | Dual and Quad Serial Flash | |
| Fabricantes | GigaDevice | |
| Logotipo |  |
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Uniform Sector
Dual and Quad Serial Flash
GD25Q128B
GD25Q128B
DATASHEET
1
Free Datasheet http://www.Datasheet4U.com
1 page  
Uniform Sector
Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
GD25Q128B
The GD25Q128B (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed of
416Mbits/s.
CONNECTION DIAGRAM
HOLD# 1
16 SCLK
VCC 2
15 SI
NC 3
14 NC
NC 4
13 NC
Top View
NC 5
12 NC
NC 6
11 NC
CS# 7
10 VSS
SO 8
9 WP#
CS# 1
SO 2
WP# 3
VSS 4
16-LEAD SOP
Top View
4
NC VCC WP# HOLD# NC NC
3
NC VSS NC SI NC NC
2
NC SCLK CS# SO NC NC
1
NC NC NC NC NC NC
Top View
8–LEAD WSON
8 VCC
7 HOLD#
6 SCLK
5 SI
PIN DESCRIPTION
Pin Name
I/O
CS# I
SO (IO1)
I/O
WP# (IO2)
I/O
VSS
SI (IO0)
I/O
SCLK
I
HOLD# (IO3)
I/O
VCC
NC
A BCDE F
24-BALL TFBGA
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
No Connect
5
Free Datasheet http://www.Datasheet4U.com
5 Page 
Uniform Sector
Dual and Quad Serial Flash
6. STATUS REGISTER
GD25Q128B
S15
SUS
S14
CMP
S13
Reserved
S12
Reserved
S11
Reserved
S10
LB
S9 S8
QE SRP1
S7 S6 S5 S4 S3 S2 S1 S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, BP0) bits are 0.
SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP
Status Register
Description
00X
Software Protected
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
010
Hardware Protected
WP#=0, the Status Register locked and can not be written to.
011
Hardware Unprotected
WP#=1, the Status Register is unlocked and can be written to
after a Write Enable command, WEL=1.
Status Register is protected and can not be written to again
1 0 X Power Supply Lock-Down(1)
until the next Power-Down, Power-Up cycle.
11X
One Time Program(1)
Status Register is permanently protected and can not be
written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
11
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet GD25Q128B.PDF ] | |
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