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HCPL-0720 の電気的特性と機能

HCPL-0720のメーカーはAgilentです、この部品の機能は「CMOS Optocoupler」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCPL-0720
部品説明 CMOS Optocoupler
メーカ Agilent
ロゴ Agilent ロゴ 




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HCPL-0720 Datasheet, HCPL-0720 PDF,ピン配置, 機能
Agilent
HCPL-0720/7720 and HCPL-0721/7721
40 ns Propagation Delay,
CMOS Optocoupler
Data Sheet
Description
Available in either an 8-pin DIP or
SO-8 package style respectively, the
HCPL-772X or HCPL-072X
optocouplers utilize the latest
CMOS IC technology to achieve
outstanding performance with very
low power consumption. The
HCPL-772X/072X require only two
bypass capacitors for complete
CMOS compatability.
Basic building blocks of the
HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED
and a CMOS detector IC. A CMOS
logic input signal controls the
LED driver IC which supplies
current to the LED. The detector
IC incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
Functional Diagram
**VDD1 1
VI 2
*3
GND1 4
LED1
SHIELD
8 VDD2**
7 NC*
IO
6 VO
5 GND2
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
* Pin 3 is the anode of the internal LED and must be left unconnected for
guaranteed data sheet performance. Pin 7 is not connected internally.
**A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and
5 and 8.
Features
• +5 V CMOS compatibility
• 20 ns maximum prop. delay skew
• High speed: 25 MBd
• 40 ns max. prop. delay
• 10 kV/µs minimum common mode
rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals
UL recognized
3750 V rms for 1 min. per
UL 1577
CSA component acceptance
notice #5
IEC/EN/DIN EN 60747-5-2
– VIORM = 630 Vpeak for
HCPL-772X option 060
– VIORM = 560 Vpeak for
HCPL-072X option 060
Applications
• Digital fieldbus isolation: CC-Link,
DeviceNet, Profibus, SDS
• AC plasma display panel level
shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
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1 Page





HCPL-0720 pdf, ピン配列
Package Outline Drawing
HCPL-772X Package with Gull Wing Surface Mount Option 300
9.65 ± 0.25
(0.380 ± 0.010)
87
65
LAND PATTERN RECOMMENDATION
1.016 (0.040)
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
12
34
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
3.56 ± 0.13
(0.140 ± 0.005)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
2.0 (0.080)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
1.080 ± 0.320
(0.043 ± 0.013)
2.54
(0.100)
BSC
0.635 ± 0.130
(0.025 ± 0.005)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 ± 0.25
(0.025 ± 0.010)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
12° NOM.
Package Outline Drawing
HCPL-072X Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION
8
3.937 ± 0.127
(0.155 ± 0.005)
PIN ONE 1
0.406 ± 0.076
(0.016 ± 0.003)
765
XXXV
YWW
234
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
1.270 BSC
(0.050)
7.49 (0.295)
1.9 (0.075)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
7°
45°
X
0.432
(0.017)
3.175 ± 0.127
(0.125 ± 0.005)
1.524
(0.060)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
0.203 ± 0.102
(0.008 ± 0.004)
0.305 MIN.
(0.012)
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
3
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3Pages


HCPL-0720 電子部品, 半導体
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage 150 V rms
for rated mains voltage 300 V rms
for rated mains voltage 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b†
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a†
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage†
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, V10 = 500 V
Symbol
VIORM
VPR
VPR
VIOTM
TS
IS,INPUT
PS,OUTPUT
RIO
HCPL-772X
Option 060
I-IV
I-IV
I-III
55/85/21
2
630
1181
945
6000
175
230
600
109
HCPL-072X
Option 060
I-IV
I-III
55/85/21
2
560
1050
Units
V peak
V peak
840 V peak
4000 V peak
150 °C
150 mA
600 mW
109
† Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section
IEC/EN/DIN EN 60747-5-2, for a detailed description.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured
by means of protective circuits.
Note: The surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter
Storage Temperature
Ambient Operating Temperature[1]
Supply Voltages
Input Voltage
Output Voltage
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
TS
TA
VDD1, VDD2
VI
VO
IO
Min.
Max.
Units
–55 125 °C
–40 +85 °C
0 6.0 Volts
–0.5
VDD1 +0.5
Volts
–0.5
VDD2 +0.5
Volts
10 mA
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Figure
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltages
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
6
Symbol
TA
VDD1, VDD2
VIH
VIL
tr, tf
Min.
–40
4.5
2.0
0.0
Max.
+85
5.5
VDD1
0.8
1.0
Units
°C
V
V
V
ms
Figure
1, 2
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共有リンク

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HCPL-0720

CMOS Optocoupler

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HCPL-0721

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HCPL-0721

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