|
|
PDF SI5355 Data sheet ( Hoja de datos )
| Número de pieza | SI5355 | |
| Descripción | ANY-FREQUENCY 1-200 MHZ QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR | |
| Fabricantes | Silicon Labs | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SI5355 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
Si5355
ANY-FREQUENCY 1–200 MHZ QUAD FREQUENCY
8-OUTPUT CLOCK GENERATOR
Features
Generates any frequency from 1 to
Excellent PSRR performance
200 MHz on each of the 4 output banks
eliminates need for external power
Eight CMOS clock outputs
supply filtering
Guaranteed 0 ppm frequency synthesis Low power: 45 mA (core)
error for any combination of frequencies Core VDD: 1.8, 2.5, or 3.3 V
25 or 27 MHz xtal or 5–200 MHz input clk Separate VDDO for each bank of
Five programmable control pins (output
outputs: 1.8, 2.5, or 3.3 V
enable, frequency select, reset)
Small size: 4x4 mm 24-QFN
Separate OEB pins to disable individual Industrial temperature range:
banks or all outputs
–40 to +85 °C
Loss of signal output
Custom versions available using
Low 50 ps (typ) pk-pk period jitter
ClockBuilder™ web utility
Phase jitter: 2 ps rms 12 kHz–20 MHz Samples available in 2 weeks
Applications
Ordering Information:
See page 17.
Pin Assignments
Printers
Audio/video
Networking
Communications
Storage
Switches/routers
Computing
Servers
OC-3/OC-12 line cards
Description
The Si5355 is a highly flexible clock generator capable of synthesizing four
completely non-integer related frequencies up to 200 MHz. The device has four
banks of outputs with each bank supporting two CMOS outputs at the same
frequency. Using Silicon Laboratories' patented MultiSynth fractional divider
technology, all outputs are guaranteed to have 0 ppm frequency synthesis error
regardless of configuration, enabling the replacement of multiple clock ICs and
crystal oscillators with a single device. Through a flexible web configuration utility
called ClockBuilder™ (www.silabs.com/ClockBuilder), factory-customized pin-
controlled Si5355 devices are available in two weeks without minimum order
quantity restrictions. The Si5355 supports up to three independent, pin-selectable
device configurations, enabling one device to replace three separate clock ICs.
Top View
24 23 22 21 20 19
XA 1
18 CLK2
XB 2
17 CLK3
P1 3
CLKIN 4
GGNNDD
16 VDDOB
15 VDDOC
P4 5
14 CLK4
P5 6
7
13 CLK5
8 9 10 11 12
Functional Block Diagram
Rev. 1.1 1/13
Copyright © 2013 by Silicon Laboratories
Si5355
Free Datasheet http://www.datasheet-pdf.com/
1 page  
Si5355
Table 3. AC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Input Clock
Clock Input Frequency
Clock Input Rise/Fall Time
Clock Input Duty Cycle
FIN
TR/TF
DC
20–80% VDD
10–90% VDD
Input tr/tf within specified
limits shown above
Clock Input Capacitance
CIN
Output Clocks
Clock Output Frequency
Clock Output Frequency Synthesis
Resolution
FO
FRES
See "3.3. Input and Output
Frequency Configuration"
on page 10
Output Load Capacitance
Clock Output Rise/Fall Time
Clock Output Rise/Fall Time
Clock Output Duty Cycle
Powerup Time
Output Enable Time
Reset Minimum Pulse Width
Output-Output Skew
Period Jitter
Cycle-Cycle Jitter*
Phase Jitter
PLL Loop Bandwidth
CL
TR/TF
TR/TF
DC
TPU
TOEB
TRESET
TSKEW
JPPKPK
JCCPK
JPH
FBW
20 to 80% VDD,
CL = 15 pF
20 to 80% VDD,
CL = 2 pF
POR to output clock valid
Outputs at same
frequency, fOUT > 5 MHz
10000 cycles*
10000 cycles*
12 kHz to 20 MHz
Interrupt Status Timing
CLKIN Loss of Signal Assert Time
CLKIN Loss of Signal Deassert
Time
tLOS
tLOS_b
LOS Rise/Fall Time (20–80%)
TR/TF CL < 10 pF, pullup < 1 k
*Note: Measured in accordance to JEDEC Standard 65.
Min
5
—
—
40
—
1
0
—
—
—
45
—
—
—
–150
—
—
—
—
—
0.01
—
Typ
—
—
—
—
2
—
0
—
—
0.45
50
—
—
—
—
50
40
2
1.6
2.6
0.2
—
Max Units
200 MHz
2.3 ns
4 ns
60 %
— pF
200 MHz
1 ppb
15 pF
2.0 ns
0.85 ns
55
2
10
200
+150
%
ms
µs
ns
ps
75 ps pk-pk
70 ps pk
— ps rms
— MHz
5 µs
1 µs
10 ns
Rev. 1.1
5
Free Datasheet http://www.datasheet-pdf.com/
5 Page 
Si5355
3.5. Output Enable
Each of the device’s four banks of CMOS clock outputs can be individually disabled using OEB_A, OEB_B,
OEB_C, and OEB_D for CLK0/1, CLK2/3, CLK4/5, and CLK6/7, respectively. Alternatively, all clock outputs can be
disabled using the master output enable OEB_ALL. When a Si5355 clock output bank is disabled, both outputs are
driven to an active low state. When one or more banks of clock outputs are enabled or disabled, clock start and
stop transitions are handled glitchlessly.
3.6. Frequency Select/Device Reset
The device frequency plan is customized using the ClockBuilder web utility. The Si5355 optionally supports up to
three unique, pin-selectable configurations per device, enabling one device to replace up to three separate clock
ICs. To select a particular frequency plan, set the FS pins as outlined below:
For custom Si5355 devices configured to support two frequency plans, the FS1 pin should be set as shown in
Table 9:
Table 9. FS1 Pin Logic for 2 Profile Devices
FS1 Profile
01
12
For custom Si5355 devices configured to support three frequency plans, the FS1 and FS0 pins should be set as
shown in Table 10:
Table 10. FS1/FS0 Pin Logic for 3 Profile Devices
FS1 FS0 Profile
0 0 Reserved
011
102
113
If a change is made to the FS pin settings, the device reset pin (RESET) must be held high for the minimum pulse
width specified in Table 3 on page 5 to change the device configuration. The output clocks will be momentarily
squelched until the device begins operation with the new frequency plan.
If the RESET pin is not selected in ClockBuilder as one of the five programmable pins, a power-on reset must be
applied for an FS pin change to take effect.
3.7. Loss-of-Signal Alarm
The Si5355 includes an interrupt pin that monitors for both loss of PLL lock (LOL) and loss of input signal (LOS)
conditions. The LOS pin is asserted whenever LOL or LOS is true. The LOS condition occurs when there is no
input clock to the device. When an input clock is removed, the LOS pin will assert, and the output may drift up to
5%. The LOL condition occurs when there is a reference present but it is off in frequency by a significant amount.
In this condition, the LOS pin will assert and the output will be disabled. When the input clock with an appropriate
frequency is reapplied, the LOS pin will de-assert. Note that the LOS pin is an open-drain output.
Rev. 1.1
11
Free
Data
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet SI5355.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SI535 | (SI535 / SI536) ULTRA LOW JITTER CRYSTAL OSCILLATOR | Silicon Labs |
| SI5350A-B | FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR |  Silicon Laboratories |
| SI5350B-B | FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR + VCXO | Silicon Laboratories |
| SI5350C-B | FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR + PLL | Silicon Laboratories |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |