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PDF VT82C693A Data sheet ( Hoja de datos )
| Número de pieza | VT82C693A | |
| Descripción | Single-Chip Slot-1 / Socket-370 North Bridge | |
| Fabricantes | VIA | |
| Logotipo |  |
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VT82C693A
LIST OF FIGURES
FIGURE 1. APOLLO PRO133 SYSTEM BLOCK DIAGRAM USING THE VT82C596B MOBILE SOUTH BRIDGE ..... 4
FIGURE 2. VT82C693A BALL DIAGRAM (TOP VIEW)........................................................................................................... 6
FIGURE 3. VT82C693A PIN LIST (NUMERICAL ORDER) ..................................................................................................... 7
FIGURE 4. VT82C693A PIN LIST (ALPHABETICAL ORDER)............................................................................................... 8
FIGURE 5. GRAPHICS APERTURE ADDRESS TRANSLATION ......................................................................................... 36
FIGURE 6. MECHANICAL SPECIFICATIONS - 492-PIN BALL GRID ARRAY PACKAGE ........................................... 46
Revision 1.0, July 22, 1999
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List of Figures
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VT82C693A
write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also
implemented for further improvement of overall system performance.
The 324-pin Ball Grid Array VT82C596B PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.2 compliant). The VT82C596B also includes an
integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter / gather capability and extension to UltraDMA-33/66 for
33/66 MB/sec transfer rate, integrated USB interface with root hub and two function ports with built-in physical layer transceivers,
Distributed DMA support, and OnNow / ACPI compliant advanced configuration and power management interface.
For sophisticated power management, the Apollo Pro133 provides independent clock stop control for the CPU / SDRAM, PCI, and
AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for the
SDRAM control signals for Suspend-to-DRAM operation. Coupled with the VT82C596B south bridge chip, a complete power
conscious PC main board can be implemented with no external TTLs.
The Apollo Pro133 chipset is ideal for high performance, high quality, high energy efficient and high integration desktop and
notebook AGP / PCI / ISA computer systems.
Revision 1.0, July 22, 1999
-5-
Overview
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