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PDF STA339BWS Data sheet ( Hoja de datos )
| Número de pieza | STA339BWS | |
| Descripción | 2.1-channel 40-watt high-efficiency digital audio system | |
| Fabricantes | STMicroelectronics | |
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STA339BWS
2.1-channel 40-watt high-efficiency digital audio system
Sound Terminal®
Features
■ Wide-range supply voltage, 4.5 V to 21.5 V
■ Three power output configurations:
– 2 channels of ternary PWM
(2 x 20 W into 8 Ω at 18 V) + PWM output
– 2 channels of ternary PWM
(2 x 20 W into 8 Ω at 18 V) + ternary stereo
line-out
– 2.1 channels of binary PWM (left, right,
LFE) (2 x 9 W into 4 Ω +1 x 20 W into 8 Ω
at 18 V)
■ FFX with 100-dB SNR and dynamic range
■ Scalable FFX modulation index
■ Selectable 32- to 192-kHz input sample rates
■ I2C control with selectable device address
■ Digital gain/attenuation +48 dB to -80 dB with
0.5-dB/step resolution
■ Soft volume update with programmable ratio
■ Individual channel and master gain/attenuation
■ Two independent DRCs configurable as a
dual-band anticlipper (B2DRC) or as
independent limiters/compressors
■ EQ-DRC for DRC based on filtered signals
■ Dedicated LFE processing for bass boosting
■ Audio presets:
– 15 preset crossover filters
– 5 preset anticlipping modes
– Preset nighttime listening mode
■ Individual channel soft/hard mute
PowerSSO-36
with exposed pad down (EPD)
■ Independent channel volume and DSP bypass
■ I2S input data interface
■ Input and output channel mapping
■ Automatic invalid input-detect mute
■ Up to 8 user-programmable biquads/channel
■ Three coefficient banks for storing EQ presets
with fast recall via I2C interface
■ Bass/treble tones and de-emphasis control
■ Selectable high-pass filter for DC blocking
■ Advanced AM interference frequency
switching and noise suppression modes
■ Selectable high- or low-bandwidth
noise-shaping topologies
■ Selectable clock input ratio
■ 96-kHz internal processing sample rate
■ Thermal overload and short-circuit protection
technology
■ Video apps: 576 x fS input mode supported
■ Pin and SW compatible with STA333BW,
STA339BW, STA559BW and STA559BWS
Table 1. Device summary
Order code
STA339BWS
STA339BWS13TR
Package
PowerSSO-36 EPD
PowerSSO-36 EPD
Packaging
Tube
Tape and reel
November 2011
Doc ID 15276 Rev 5
1/76
www.st.com
76
Free Datasheet http://www.datasheet4u.com/
1 page  
STA339BWS
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Left and right processing, section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Left and right processing, section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
B2DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
EQDRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Output configuration for stereo BTL mode (RL = 8 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Doc ID 15276 Rev 5
5/76
5 Page 
STA339BWS
Pin connections
Table 2. Pin description (continued)
Pin Type
Name
Description
11 Power VCC1
12 GND GND1
13 O
OUT1A
14 GND GND_REG
Power positive supply
Power negative supply
Output half-bridge channel 1A
Internal ground reference
15 Power VDD
Internal 3.3 V reference voltage
16 I
CONFIG
Parallel mode command
17 O
OUT3B / FFX3B PWM out channel 3B / external bridge driver
18 O
OUT3A / FFX3A PWM out channel 3A / external bridge driver
19 O
EAPD / OUT4B Power down for external bridge / PWM out channel 4B
20
I/O
TWARN / OUT4A
Thermal warning from external bridge (pull-up when input)
/ PWM out channel 4A
21 Power VDD_DIG
22 GND GND_DIG
23 I
PWRDN
24 Power VDD_PLL
Digital supply voltage
Digital ground
Power down (pull-up)
Positive supply for PLL
25 I
FILTER_PLL
Connection to PLL filter
26 GND GND_PLL
Negative supply for PLL
27 I
28 I
29 I
30 I
XTI
BICKI
LRCKI
SDI
PLL input clock
I2S serial clock
I2S left/right clock
I2S serial data channels 1 and 2
31 I
RESET
Reset (pull-up)
32 O
INT_LINE
33 I/O SDA
34 I
SCL
Fault interrupt
I2C serial data
I2C serial clock
35 GND GND_DIG
Digital ground
36 Power VDD_DIG
Digital supply voltage
- - EP
Exposed pad for PCB heatsink, to be connected to GND
Doc ID 15276 Rev 5
11/76
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet STA339BWS.PDF ] | |
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