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PDF STA339BW Data sheet ( Hoja de datos )
| Número de pieza | STA339BW | |
| Descripción | 2.1-channel high-efficiency digital audio system | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STA339BW
2.1-channel high-efficiency digital audio system
Features
Wide voltage supply range
– 5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
3 power output configurations
– 2 channels of ternary PWM (stereo mode)
(2 x 20 W into 8 Ω at 18 V)
– 3 channels - left, right using binary and LFE
using ternary PWM (2.1 mode) (2 x 9 W +
1 x 20 W into 2 x 4 Ω, 1 x 8 Ω at 18 V)
– 2 channels of ternary PWM (2 x 20 W) +
stereo lineout ternary
2.1 channels of 24-bit FFX® 100 dB SNR and
dynamic range
Selectable 32 to 192 kHz input sample rates
I2C control with selectable device address
Digital gain/attenuation +48 dB to -80 dB with
0.5 dB/step resolution
Soft volume update with programmable ratio
Individual channel and master gain/attenuation
Two independent DRC configurable as a
dual-band anti-clipper (B2DRC) or as
independent limiters/compressors
EQ-DRC for DRC based on filtered signals
Dedicated LFE processing for bass boosting
with 0.5 dB/step resolution
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset night-time listening mode
Individual channel and master soft/hard mute
PowerSSO-36 (slug down)
Independent channel volume and DSP bypass
Automatic zero-detect mute
Automatic invalid input-detect mute
2-channel I2S input data interface
Input and output channel mapping
Up to 8 user-programmable biquads per
channel with 28-bit resolution
3 coefficient banks for EQ presets storing with
fast recall via I2C interface
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency
switching and noise suppression modes
Selectable high- or low-bandwidth
noise-shaping topologies
Variable max power correction for lower
full-power THD
Selectable clock input ratio
96 kHz internal processing sample rate, 24 to
28-bit precision
Thermal overload and short-circuit protection
embedded
Video apps: 576 * fS input mode supported
Fully compatible with STA339BWS.
Table 1.
Device summary
Order code
STA339BW
STA339BWTR
Package
PowerSSO-36 slug down
PowerSSO-36 slug down
Packaging
Tube
Tape and reel
August 2010
Doc ID 15251 Rev 5
1/77
www.st.com
77
Free Datasheet http://www.datasheet4u.com/
1 page  
STA339BW
Contents
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.11.6 Limiter 1 Extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 55
6.11.7 Limiter 2 Extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . . ) 56
6.11.8 Limiter 2 Extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 56
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 56
6.12.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.12.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.12.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.12.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.12.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.12.19 Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.12.20 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.12.21 Overcurrent postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 63
Variable distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . 63
Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 64
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 65
Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 65
6.18.1 Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.18.2 EQ DRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.18.3 Extended post scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.18.4 Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.18.5 Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Doc ID 15251 Rev 5
5/77
5 Page 
STA339BW
1.1 Block diagram
Figure 1. Block diagram
I2S
interface
I2C
Volume
control
FFX
Power
control
PLL
Digital DSP
Description
Protection
current/thermal
Channel
1A
Logic
Channel
1B
Regulators
Bias
Channel
2A
Channel
2B
Power
Doc ID 15251 Rev 5
11/77
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STA339BW.PDF ] | |
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