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GD25Q80BSIG の電気的特性と機能

GD25Q80BSIGのメーカーはGigaDeviceです、この部品の機能は「Dual and Quad Serial Flash」です。


製品の詳細 ( Datasheet PDF )

部品番号 GD25Q80BSIG
部品説明 Dual and Quad Serial Flash
メーカ GigaDevice
ロゴ GigaDevice ロゴ 




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GD25Q80BSIG Datasheet, GD25Q80BSIG PDF,ピン配置, 機能
25Q80BSIG
FEATURES
8M-bit Serial Flash
-1024K-byte
-256 bytes per programmable page
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 180Mbits/s
-Quad I/O Data transfer up to 360Mbits/s
Program/Erase Speed
-Page Program time: 0.7ms typical
-Sector Erase time: 100ms typical
-Block Erase time: 0.3/0.4/0.8s typical
-Chip Erase time: 8s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64/128K-byte
Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
Minimum 100,000 Program/Erase Cycles
Note: 1.Please contact Gigadevice for details
Advanced security Features(1)
-16-Bit Customer ID
-Security Architecture
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
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GENERAL DESCRIPTION
The GD25Q80 (8M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of
360Mbits/s.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1
datasheet pdf - http://www.DataSheet4U.net/

1 Page





GD25Q80BSIG pdf, ピン配列
Uniform Sector
Dual and Quad Serial Flash
GD25Q80
MEMORY ORGANIZATION
Each device has
Each block has
1M 128/64/32K
4K 512/256/128
256 32/16/8
8/16/32
-
Each sector has
4K
16
-
-
Each page has
256
-
-
-
bytes
pages
sectors
blocks
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25Q80 64K Bytes Block Sector Architecture
Block
Sector
15
14
……
……
2
1
0
255
……
240
239
……
224
……
……
……
……
……
……
47
……
32
31
……
16
15
……
0
Address range
0FF000H
……
0F0000H
0EF000H
……
0E0000H
……
……
……
……
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……
……
02F000H
……
020000H
01F000H
……
010000H
00F000H
……
000000H
0FFFFFH
……
0F0FFFH
0EFFFFH
……
0E0FFFH
……
……
……
……
……
……
02FFFFH
……
020FFFH
01FFFFH
……
010FFFH
00FFFFH
……
000FFFH
3
datasheet pdf - http://www.DataSheet4U.net/


3Pages


GD25Q80BSIG 電子部品, 半導体
Uniform Sector
Dual and Quad Serial Flash
GD25Q80
Status Register
S15-S10
S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Reserved
QE SRP1 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, BP0) bits are 0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
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programmable protection.
SRP1 SRP0 #WP
Status Register
Description
00X
Software Protected
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
010
Hardware Protected
WP#=0, the Status Register locked and can not be written to.
011
Hardware Unprotected
WP#=1, the Status Register is unlocked and can be written to
after a Write Enable command, WEL=1.
Status Register is protected and can not be written to again
1 0 X Power Supply Lock-Down(1)
until the next Power-Down, Power-Up cycle.
11X
One Time Program
Status Register is permanently protected and can not be
written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground)
6
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6 Page



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部品番号部品説明メーカ
GD25Q80BSIG

Dual and Quad Serial Flash

GigaDevice
GigaDevice


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